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2eda391bdf
That's OK if you know the datasheet well, but for casual readers some comments are really helpful. I'm not sure whether we want to disable hardware flash access forever without enabling it again on shutdown. A few other places made me wonder as well. I've added FIXME comments in those places. Corresponding to flashrom svn r1046. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Andrew Morgan <ziltro@ziltro.com>
116 lines
3.0 KiB
C
116 lines
3.0 KiB
C
/*
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* This file is part of the flashrom project.
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*
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* Copyright (C) 2009 Joerg Fischer <turboj@gmx.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#if defined(__i386__) || defined(__x86_64__)
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#include <stdlib.h>
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#include "flash.h"
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#define PCI_VENDOR_ID_REALTEK 0x10ec
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#define PCI_VENDOR_ID_SMC1211 0x1113
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#define BIOS_ROM_ADDR 0xD4
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#define BIOS_ROM_DATA 0xD7
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struct pcidev_status nics_realtek[] = {
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{0x10ec, 0x8139, OK, "Realtek", "RTL8139/8139C/8139C+"},
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{},
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};
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struct pcidev_status nics_realteksmc1211[] = {
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{0x1113, 0x1211, OK, "SMC2", "1211TX"}, /* RTL8139 clone */
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{},
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};
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int nicrealtek_init(void)
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{
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get_io_perms();
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io_base_addr = pcidev_init(PCI_VENDOR_ID_REALTEK, PCI_BASE_ADDRESS_0,
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nics_realtek, programmer_param);
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buses_supported = CHIP_BUSTYPE_PARALLEL;
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return 0;
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}
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int nicsmc1211_init(void)
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{
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get_io_perms();
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io_base_addr = pcidev_init(PCI_VENDOR_ID_SMC1211, PCI_BASE_ADDRESS_0,
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nics_realteksmc1211, programmer_param);
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buses_supported = CHIP_BUSTYPE_PARALLEL;
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return 0;
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}
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int nicrealtek_shutdown(void)
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{
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/* FIXME: We forgot to disable software access again. */
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free(programmer_param);
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pci_cleanup(pacc);
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release_io_perms();
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return 0;
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}
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void nicrealtek_chip_writeb(uint8_t val, chipaddr addr)
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{
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/* Output addr and data, set WE to 0, set OE to 1, set CS to 0,
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* enable software access.
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*/
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OUTL(((uint32_t)addr & 0x01FFFF) | 0x0A0000 | (val << 24),
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io_base_addr + BIOS_ROM_ADDR);
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/* Output addr and data, set WE to 1, set OE to 1, set CS to 1,
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* enable software access.
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*/
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OUTL(((uint32_t)addr & 0x01FFFF) | 0x1E0000 | (val << 24),
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io_base_addr + BIOS_ROM_ADDR);
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}
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uint8_t nicrealtek_chip_readb(const chipaddr addr)
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{
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uint8_t val;
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/* FIXME: Can we skip reading the old data and simply use 0? */
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/* Read old data. */
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val = INB(io_base_addr + BIOS_ROM_DATA);
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/* Output new addr and old data, set WE to 1, set OE to 0, set CS to 0,
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* enable software access.
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*/
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OUTL(((uint32_t)addr & 0x01FFFF) | 0x060000 | (val << 24),
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io_base_addr + BIOS_ROM_ADDR);
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/* Read new data. */
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val = INB(io_base_addr + BIOS_ROM_DATA);
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/* Output addr and new data, set WE to 1, set OE to 1, set CS to 1,
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* enable software access.
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*/
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OUTL(((uint32_t)addr & 0x01FFFF) | 0x1E0000 | (val << 24),
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io_base_addr + BIOS_ROM_ADDR);
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return val;
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}
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#else
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#error PCI port I/O access is not supported on this architecture yet.
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#endif
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