mirror of
https://review.coreboot.org/flashrom.git
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32508eb304
Move hwaccess.h #include from flash.h to individual drivers. libflashrom users need flash.h, but they do not care about hwaccess.h and should not see its definitions because they may conflict with other hardware access functions and #defines used by the libflashrom user. Corresponding to flashrom svn r1549. Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
105 lines
2.9 KiB
C
105 lines
2.9 KiB
C
/*
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* This file is part of the flashrom project.
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*
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* Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#if defined(__i386__) || defined(__x86_64__)
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#include <stdlib.h>
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#include <string.h>
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#include "flash.h"
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#include "programmer.h"
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#include "hwaccess.h"
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#define BIOS_ROM_ADDR 0x90
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#define BIOS_ROM_DATA 0x94
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#define REG_FLASH_ACCESS 0x58
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#define PCI_VENDOR_ID_HPT 0x1103
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const struct pcidev_status ata_hpt[] = {
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{0x1103, 0x0004, NT, "Highpoint", "HPT366/368/370/370A/372/372N"},
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{0x1103, 0x0005, NT, "Highpoint", "HPT372A/372N"},
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{0x1103, 0x0006, NT, "Highpoint", "HPT302/302N"},
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{},
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};
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static void atahpt_chip_writeb(const struct flashctx *flash, uint8_t val,
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chipaddr addr);
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static uint8_t atahpt_chip_readb(const struct flashctx *flash,
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const chipaddr addr);
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static const struct par_programmer par_programmer_atahpt = {
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.chip_readb = atahpt_chip_readb,
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.chip_readw = fallback_chip_readw,
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.chip_readl = fallback_chip_readl,
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.chip_readn = fallback_chip_readn,
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.chip_writeb = atahpt_chip_writeb,
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.chip_writew = fallback_chip_writew,
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.chip_writel = fallback_chip_writel,
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.chip_writen = fallback_chip_writen,
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};
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static int atahpt_shutdown(void *data)
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{
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/* Flash access is disabled automatically by PCI restore. */
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pci_cleanup(pacc);
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release_io_perms();
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return 0;
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}
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int atahpt_init(void)
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{
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uint32_t reg32;
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get_io_perms();
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io_base_addr = pcidev_init(PCI_BASE_ADDRESS_4, ata_hpt);
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/* Enable flash access. */
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reg32 = pci_read_long(pcidev_dev, REG_FLASH_ACCESS);
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reg32 |= (1 << 24);
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rpci_write_long(pcidev_dev, REG_FLASH_ACCESS, reg32);
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if (register_shutdown(atahpt_shutdown, NULL))
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return 1;
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register_par_programmer(&par_programmer_atahpt, BUS_PARALLEL);
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return 0;
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}
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static void atahpt_chip_writeb(const struct flashctx *flash, uint8_t val,
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chipaddr addr)
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{
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OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR);
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OUTB(val, io_base_addr + BIOS_ROM_DATA);
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}
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static uint8_t atahpt_chip_readb(const struct flashctx *flash,
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const chipaddr addr)
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{
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OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR);
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return INB(io_base_addr + BIOS_ROM_DATA);
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}
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#else
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#error PCI port I/O access is not supported on this architecture yet.
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#endif
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