mirror of
https://review.coreboot.org/flashrom.git
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bcf6109a76
Apart from the strange ID (using Sanyo's vendor ID 0x62) the main difference from the plain SST25WF series is that they lack op codes 0xAD (AAI Word program) and 0x52 (32K erase). The smallest version does not support dual I/O operations either. SST25WF080B was tested under Linux with spidev. Corresponding to flashrom svn r1901. Tested-by: Ben Gardner <bgardner@wabtec.com> Signed-off-by: Ben Gardner <bgardner@wabtec.com> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
739 lines
25 KiB
C
739 lines
25 KiB
C
/*
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* This file is part of the flashrom project.
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* It handles everything related to status registers of the JEDEC family 25.
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*
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* Copyright (C) 2007, 2008, 2009, 2010 Carl-Daniel Hailfinger
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* Copyright (C) 2008 coresystems GmbH
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* Copyright (C) 2008 Ronald Hoogenboom <ronald@zonnet.nl>
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* Copyright (C) 2012 Stefan Tauner
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "flash.h"
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#include "chipdrivers.h"
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#include "spi.h"
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/* === Generic functions === */
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int spi_write_status_enable(struct flashctx *flash)
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{
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static const unsigned char cmd[JEDEC_EWSR_OUTSIZE] = { JEDEC_EWSR };
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int result;
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/* Send EWSR (Enable Write Status Register). */
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result = spi_send_command(flash, sizeof(cmd), JEDEC_EWSR_INSIZE, cmd, NULL);
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if (result)
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msg_cerr("%s failed\n", __func__);
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return result;
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}
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static int spi_write_status_register_flag(struct flashctx *flash, int status, const unsigned char enable_opcode)
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{
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int result;
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int i = 0;
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/*
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* WRSR requires either EWSR or WREN depending on chip type.
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* The code below relies on the fact hat EWSR and WREN have the same
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* INSIZE and OUTSIZE.
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*/
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struct spi_command cmds[] = {
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{
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.writecnt = JEDEC_WREN_OUTSIZE,
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.writearr = (const unsigned char[]){ enable_opcode },
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.readcnt = 0,
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.readarr = NULL,
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}, {
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.writecnt = JEDEC_WRSR_OUTSIZE,
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.writearr = (const unsigned char[]){ JEDEC_WRSR, (unsigned char) status },
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.readcnt = 0,
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.readarr = NULL,
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}, {
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.writecnt = 0,
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.writearr = NULL,
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.readcnt = 0,
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.readarr = NULL,
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}};
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result = spi_send_multicommand(flash, cmds);
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if (result) {
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msg_cerr("%s failed during command execution\n", __func__);
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/* No point in waiting for the command to complete if execution
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* failed.
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*/
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return result;
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}
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/* WRSR performs a self-timed erase before the changes take effect.
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* This may take 50-85 ms in most cases, and some chips apparently
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* allow running RDSR only once. Therefore pick an initial delay of
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* 100 ms, then wait in 10 ms steps until a total of 5 s have elapsed.
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*/
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programmer_delay(100 * 1000);
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while (spi_read_status_register(flash) & SPI_SR_WIP) {
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if (++i > 490) {
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msg_cerr("Error: WIP bit after WRSR never cleared\n");
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return TIMEOUT_ERROR;
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}
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programmer_delay(10 * 1000);
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}
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return 0;
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}
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int spi_write_status_register(struct flashctx *flash, int status)
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{
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int feature_bits = flash->chip->feature_bits;
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int ret = 1;
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if (!(feature_bits & (FEATURE_WRSR_WREN | FEATURE_WRSR_EWSR))) {
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msg_cdbg("Missing status register write definition, assuming "
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"EWSR is needed\n");
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feature_bits |= FEATURE_WRSR_EWSR;
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}
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if (feature_bits & FEATURE_WRSR_WREN)
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ret = spi_write_status_register_flag(flash, status, JEDEC_WREN);
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if (ret && (feature_bits & FEATURE_WRSR_EWSR))
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ret = spi_write_status_register_flag(flash, status, JEDEC_EWSR);
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return ret;
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}
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uint8_t spi_read_status_register(struct flashctx *flash)
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{
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static const unsigned char cmd[JEDEC_RDSR_OUTSIZE] = { JEDEC_RDSR };
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/* FIXME: No workarounds for driver/hardware bugs in generic code. */
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unsigned char readarr[2]; /* JEDEC_RDSR_INSIZE=1 but wbsio needs 2 */
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int ret;
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/* Read Status Register */
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ret = spi_send_command(flash, sizeof(cmd), sizeof(readarr), cmd, readarr);
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if (ret)
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msg_cerr("RDSR failed!\n");
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return readarr[0];
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}
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/* A generic block protection disable.
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* Tests if a protection is enabled with the block protection mask (bp_mask) and returns success otherwise.
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* Tests if the register bits are locked with the lock_mask (lock_mask).
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* Tests if a hardware protection is active (i.e. low pin/high bit value) with the write protection mask
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* (wp_mask) and bails out in that case.
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* If there are register lock bits set we try to disable them by unsetting those bits of the previous register
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* contents that are set in the lock_mask. We then check if removing the lock bits has worked and continue as if
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* they never had been engaged:
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* If the lock bits are out of the way try to disable engaged protections.
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* To support uncommon global unprotects (e.g. on most AT2[56]xx1(A)) unprotect_mask can be used to force
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* bits to 0 additionally to those set in bp_mask and lock_mask. Only bits set in unprotect_mask are potentially
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* preserved when doing the final unprotect.
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*
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* To sum up:
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* bp_mask: set those bits that correspond to the bits in the status register that indicate an active protection
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* (which should be unset after this function returns).
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* lock_mask: set the bits that correspond to the bits that lock changing the bits above.
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* wp_mask: set the bits that correspond to bits indicating non-software revocable protections.
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* unprotect_mask: set the bits that should be preserved if possible when unprotecting.
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*/
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static int spi_disable_blockprotect_generic(struct flashctx *flash, uint8_t bp_mask, uint8_t lock_mask, uint8_t wp_mask, uint8_t unprotect_mask)
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{
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uint8_t status;
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int result;
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status = spi_read_status_register(flash);
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if ((status & bp_mask) == 0) {
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msg_cdbg2("Block protection is disabled.\n");
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return 0;
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}
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msg_cdbg("Some block protection in effect, disabling... ");
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if ((status & lock_mask) != 0) {
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msg_cdbg("\n\tNeed to disable the register lock first... ");
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if (wp_mask != 0 && (status & wp_mask) == 0) {
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msg_cerr("Hardware protection is active, disabling write protection is impossible.\n");
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return 1;
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}
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/* All bits except the register lock bit (often called SPRL, SRWD, WPEN) are readonly. */
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result = spi_write_status_register(flash, status & ~lock_mask);
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if (result) {
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msg_cerr("spi_write_status_register failed.\n");
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return result;
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}
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status = spi_read_status_register(flash);
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if ((status & lock_mask) != 0) {
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msg_cerr("Unsetting lock bit(s) failed.\n");
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return 1;
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}
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msg_cdbg("done.\n");
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}
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/* Global unprotect. Make sure to mask the register lock bit as well. */
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result = spi_write_status_register(flash, status & ~(bp_mask | lock_mask) & unprotect_mask);
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if (result) {
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msg_cerr("spi_write_status_register failed.\n");
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return result;
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}
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status = spi_read_status_register(flash);
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if ((status & bp_mask) != 0) {
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msg_cerr("Block protection could not be disabled!\n");
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flash->chip->printlock(flash);
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return 1;
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}
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msg_cdbg("disabled.\n");
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return 0;
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}
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/* A common block protection disable that tries to unset the status register bits masked by 0x3C. */
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int spi_disable_blockprotect(struct flashctx *flash)
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{
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return spi_disable_blockprotect_generic(flash, 0x3C, 0, 0, 0xFF);
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}
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/* A common block protection disable that tries to unset the status register bits masked by 0x0C (BP0-1) and
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* protected/locked by bit #7. Useful when bits 4-5 may be non-0). */
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int spi_disable_blockprotect_bp1_srwd(struct flashctx *flash)
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{
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return spi_disable_blockprotect_generic(flash, 0x0C, 1 << 7, 0, 0xFF);
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}
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/* A common block protection disable that tries to unset the status register bits masked by 0x1C (BP0-2) and
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* protected/locked by bit #7. Useful when bit #5 is neither a protection bit nor reserved (and hence possibly
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* non-0). */
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int spi_disable_blockprotect_bp2_srwd(struct flashctx *flash)
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{
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return spi_disable_blockprotect_generic(flash, 0x1C, 1 << 7, 0, 0xFF);
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}
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/* A common block protection disable that tries to unset the status register bits masked by 0x3C (BP0-3) and
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* protected/locked by bit #7. */
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int spi_disable_blockprotect_bp3_srwd(struct flashctx *flash)
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{
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return spi_disable_blockprotect_generic(flash, 0x3C, 1 << 7, 0, 0xFF);
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}
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/* A common block protection disable that tries to unset the status register bits masked by 0x7C (BP0-4) and
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* protected/locked by bit #7. */
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int spi_disable_blockprotect_bp4_srwd(struct flashctx *flash)
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{
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return spi_disable_blockprotect_generic(flash, 0x7C, 1 << 7, 0, 0xFF);
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}
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static void spi_prettyprint_status_register_hex(uint8_t status)
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{
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msg_cdbg("Chip status register is 0x%02x.\n", status);
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}
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/* Common highest bit: Status Register Write Disable (SRWD) or Status Register Protect (SRP). */
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static void spi_prettyprint_status_register_srwd(uint8_t status)
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{
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msg_cdbg("Chip status register: Status Register Write Disable (SRWD, SRP, ...) is %sset\n",
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(status & (1 << 7)) ? "" : "not ");
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}
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/* Common highest bit: Block Protect Write Disable (BPL). */
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static void spi_prettyprint_status_register_bpl(uint8_t status)
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{
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msg_cdbg("Chip status register: Block Protect Write Disable (BPL) is %sset\n",
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(status & (1 << 7)) ? "" : "not ");
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}
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/* Common lowest 2 bits: WEL and WIP. */
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static void spi_prettyprint_status_register_welwip(uint8_t status)
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{
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msg_cdbg("Chip status register: Write Enable Latch (WEL) is %sset\n",
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(status & (1 << 1)) ? "" : "not ");
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msg_cdbg("Chip status register: Write In Progress (WIP/BUSY) is %sset\n",
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(status & (1 << 0)) ? "" : "not ");
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}
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/* Common block protection (BP) bits. */
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static void spi_prettyprint_status_register_bp(uint8_t status, int bp)
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{
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switch (bp) {
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/* Fall through. */
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case 4:
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msg_cdbg("Chip status register: Block Protect 4 (BP4) is %sset\n",
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(status & (1 << 6)) ? "" : "not ");
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case 3:
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msg_cdbg("Chip status register: Block Protect 3 (BP3) is %sset\n",
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(status & (1 << 5)) ? "" : "not ");
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case 2:
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msg_cdbg("Chip status register: Block Protect 2 (BP2) is %sset\n",
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(status & (1 << 4)) ? "" : "not ");
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case 1:
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msg_cdbg("Chip status register: Block Protect 1 (BP1) is %sset\n",
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(status & (1 << 3)) ? "" : "not ");
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case 0:
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msg_cdbg("Chip status register: Block Protect 0 (BP0) is %sset\n",
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(status & (1 << 2)) ? "" : "not ");
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}
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}
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/* Unnamed bits. */
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void spi_prettyprint_status_register_bit(uint8_t status, int bit)
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{
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msg_cdbg("Chip status register: Bit %i is %sset\n", bit, (status & (1 << bit)) ? "" : "not ");
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}
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int spi_prettyprint_status_register_plain(struct flashctx *flash)
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{
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uint8_t status = spi_read_status_register(flash);
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spi_prettyprint_status_register_hex(status);
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return 0;
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}
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/* Print the plain hex value and the welwip bits only. */
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int spi_prettyprint_status_register_default_welwip(struct flashctx *flash)
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{
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uint8_t status = spi_read_status_register(flash);
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spi_prettyprint_status_register_hex(status);
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spi_prettyprint_status_register_welwip(status);
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return 0;
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}
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/* Works for many chips of the
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* AMIC A25L series
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* and MX MX25L512
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*/
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int spi_prettyprint_status_register_bp1_srwd(struct flashctx *flash)
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{
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uint8_t status = spi_read_status_register(flash);
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spi_prettyprint_status_register_hex(status);
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spi_prettyprint_status_register_srwd(status);
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spi_prettyprint_status_register_bit(status, 6);
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spi_prettyprint_status_register_bit(status, 5);
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spi_prettyprint_status_register_bit(status, 4);
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spi_prettyprint_status_register_bp(status, 1);
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spi_prettyprint_status_register_welwip(status);
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return 0;
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}
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/* Works for many chips of the
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* AMIC A25L series
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* PMC Pm25LD series
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*/
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int spi_prettyprint_status_register_bp2_srwd(struct flashctx *flash)
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{
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uint8_t status = spi_read_status_register(flash);
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spi_prettyprint_status_register_hex(status);
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spi_prettyprint_status_register_srwd(status);
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spi_prettyprint_status_register_bit(status, 6);
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spi_prettyprint_status_register_bit(status, 5);
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spi_prettyprint_status_register_bp(status, 2);
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spi_prettyprint_status_register_welwip(status);
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return 0;
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}
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/* Works for many chips of the
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* ST M25P series
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* MX MX25L series
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*/
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int spi_prettyprint_status_register_bp3_srwd(struct flashctx *flash)
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{
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uint8_t status = spi_read_status_register(flash);
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spi_prettyprint_status_register_hex(status);
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spi_prettyprint_status_register_srwd(status);
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spi_prettyprint_status_register_bit(status, 6);
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spi_prettyprint_status_register_bp(status, 3);
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spi_prettyprint_status_register_welwip(status);
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return 0;
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}
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int spi_prettyprint_status_register_bp4_srwd(struct flashctx *flash)
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{
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uint8_t status = spi_read_status_register(flash);
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spi_prettyprint_status_register_hex(status);
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spi_prettyprint_status_register_srwd(status);
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spi_prettyprint_status_register_bp(status, 4);
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spi_prettyprint_status_register_welwip(status);
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return 0;
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}
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int spi_prettyprint_status_register_bp2_bpl(struct flashctx *flash)
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{
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uint8_t status = spi_read_status_register(flash);
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spi_prettyprint_status_register_hex(status);
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spi_prettyprint_status_register_bpl(status);
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spi_prettyprint_status_register_bit(status, 6);
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spi_prettyprint_status_register_bit(status, 5);
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spi_prettyprint_status_register_bp(status, 2);
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spi_prettyprint_status_register_welwip(status);
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return 0;
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}
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int spi_prettyprint_status_register_bp2_tb_bpl(struct flashctx *flash)
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{
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uint8_t status = spi_read_status_register(flash);
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spi_prettyprint_status_register_hex(status);
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spi_prettyprint_status_register_bpl(status);
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spi_prettyprint_status_register_bit(status, 6);
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msg_cdbg("Chip status register: Top/Bottom (TB) is %s\n", (status & (1 << 5)) ? "bottom" : "top");
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spi_prettyprint_status_register_bp(status, 2);
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spi_prettyprint_status_register_welwip(status);
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return 0;
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}
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/* === Amic ===
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* FIXME: spi_disable_blockprotect is incorrect but works fine for chips using
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* spi_prettyprint_status_register_bp1_srwd or
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* spi_prettyprint_status_register_bp2_srwd.
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* FIXME: spi_disable_blockprotect is incorrect and will fail for chips using
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* spi_prettyprint_status_register_amic_a25l032 if those have locks controlled
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* by the second status register.
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*/
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int spi_prettyprint_status_register_amic_a25l032(struct flashctx *flash)
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{
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uint8_t status = spi_read_status_register(flash);
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spi_prettyprint_status_register_hex(status);
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spi_prettyprint_status_register_srwd(status);
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msg_cdbg("Chip status register: Sector Protect Size (SEC) is %i KB\n", (status & (1 << 6)) ? 4 : 64);
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msg_cdbg("Chip status register: Top/Bottom (TB) is %s\n", (status & (1 << 5)) ? "bottom" : "top");
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spi_prettyprint_status_register_bp(status, 2);
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spi_prettyprint_status_register_welwip(status);
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msg_cdbg("Chip status register 2 is NOT decoded!\n");
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return 0;
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}
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/* === Atmel === */
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static void spi_prettyprint_status_register_atmel_at25_wpen(uint8_t status)
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{
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msg_cdbg("Chip status register: Write Protect Enable (WPEN) is %sset\n",
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(status & (1 << 7)) ? "" : "not ");
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}
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static void spi_prettyprint_status_register_atmel_at25_srpl(uint8_t status)
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{
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msg_cdbg("Chip status register: Sector Protection Register Lock (SRPL) is %sset\n",
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(status & (1 << 7)) ? "" : "not ");
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}
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static void spi_prettyprint_status_register_atmel_at25_epewpp(uint8_t status)
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{
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msg_cdbg("Chip status register: Erase/Program Error (EPE) is %sset\n",
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(status & (1 << 5)) ? "" : "not ");
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msg_cdbg("Chip status register: WP# pin (WPP) is %sasserted\n",
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(status & (1 << 4)) ? "not " : "");
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}
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|
|
static void spi_prettyprint_status_register_atmel_at25_swp(uint8_t status)
|
|
{
|
|
msg_cdbg("Chip status register: Software Protection Status (SWP): ");
|
|
switch (status & (3 << 2)) {
|
|
case 0x0 << 2:
|
|
msg_cdbg("no sectors are protected\n");
|
|
break;
|
|
case 0x1 << 2:
|
|
msg_cdbg("some sectors are protected\n");
|
|
/* FIXME: Read individual Sector Protection Registers. */
|
|
break;
|
|
case 0x3 << 2:
|
|
msg_cdbg("all sectors are protected\n");
|
|
break;
|
|
default:
|
|
msg_cdbg("reserved for future use\n");
|
|
break;
|
|
}
|
|
}
|
|
|
|
int spi_prettyprint_status_register_at25df(struct flashctx *flash)
|
|
{
|
|
uint8_t status = spi_read_status_register(flash);
|
|
spi_prettyprint_status_register_hex(status);
|
|
|
|
spi_prettyprint_status_register_atmel_at25_srpl(status);
|
|
spi_prettyprint_status_register_bit(status, 6);
|
|
spi_prettyprint_status_register_atmel_at25_epewpp(status);
|
|
spi_prettyprint_status_register_atmel_at25_swp(status);
|
|
spi_prettyprint_status_register_welwip(status);
|
|
return 0;
|
|
}
|
|
|
|
int spi_prettyprint_status_register_at25df_sec(struct flashctx *flash)
|
|
{
|
|
/* FIXME: We should check the security lockdown. */
|
|
msg_cdbg("Ignoring security lockdown (if present)\n");
|
|
msg_cdbg("Ignoring status register byte 2\n");
|
|
return spi_prettyprint_status_register_at25df(flash);
|
|
}
|
|
|
|
/* used for AT25F512, AT25F1024(A), AT25F2048 */
|
|
int spi_prettyprint_status_register_at25f(struct flashctx *flash)
|
|
{
|
|
uint8_t status;
|
|
|
|
status = spi_read_status_register(flash);
|
|
spi_prettyprint_status_register_hex(status);
|
|
|
|
spi_prettyprint_status_register_atmel_at25_wpen(status);
|
|
spi_prettyprint_status_register_bit(status, 6);
|
|
spi_prettyprint_status_register_bit(status, 5);
|
|
spi_prettyprint_status_register_bit(status, 4);
|
|
spi_prettyprint_status_register_bp(status, 1);
|
|
spi_prettyprint_status_register_welwip(status);
|
|
return 0;
|
|
}
|
|
|
|
int spi_prettyprint_status_register_at25f512a(struct flashctx *flash)
|
|
{
|
|
uint8_t status;
|
|
|
|
status = spi_read_status_register(flash);
|
|
spi_prettyprint_status_register_hex(status);
|
|
|
|
spi_prettyprint_status_register_atmel_at25_wpen(status);
|
|
spi_prettyprint_status_register_bit(status, 6);
|
|
spi_prettyprint_status_register_bit(status, 5);
|
|
spi_prettyprint_status_register_bit(status, 4);
|
|
spi_prettyprint_status_register_bit(status, 3);
|
|
spi_prettyprint_status_register_bp(status, 0);
|
|
spi_prettyprint_status_register_welwip(status);
|
|
return 0;
|
|
}
|
|
|
|
int spi_prettyprint_status_register_at25f512b(struct flashctx *flash)
|
|
{
|
|
uint8_t status = spi_read_status_register(flash);
|
|
spi_prettyprint_status_register_hex(status);
|
|
|
|
spi_prettyprint_status_register_atmel_at25_srpl(status);
|
|
spi_prettyprint_status_register_bit(status, 6);
|
|
spi_prettyprint_status_register_atmel_at25_epewpp(status);
|
|
spi_prettyprint_status_register_bit(status, 3);
|
|
spi_prettyprint_status_register_bp(status, 0);
|
|
spi_prettyprint_status_register_welwip(status);
|
|
return 0;
|
|
}
|
|
|
|
int spi_prettyprint_status_register_at25f4096(struct flashctx *flash)
|
|
{
|
|
uint8_t status;
|
|
|
|
status = spi_read_status_register(flash);
|
|
spi_prettyprint_status_register_hex(status);
|
|
|
|
spi_prettyprint_status_register_atmel_at25_wpen(status);
|
|
spi_prettyprint_status_register_bit(status, 6);
|
|
spi_prettyprint_status_register_bit(status, 5);
|
|
spi_prettyprint_status_register_bp(status, 2);
|
|
spi_prettyprint_status_register_welwip(status);
|
|
return 0;
|
|
}
|
|
|
|
int spi_prettyprint_status_register_at25fs010(struct flashctx *flash)
|
|
{
|
|
uint8_t status = spi_read_status_register(flash);
|
|
spi_prettyprint_status_register_hex(status);
|
|
|
|
spi_prettyprint_status_register_atmel_at25_wpen(status);
|
|
msg_cdbg("Chip status register: Bit 6 / Block Protect 4 (BP4) is "
|
|
"%sset\n", (status & (1 << 6)) ? "" : "not ");
|
|
msg_cdbg("Chip status register: Bit 5 / Block Protect 3 (BP3) is "
|
|
"%sset\n", (status & (1 << 5)) ? "" : "not ");
|
|
spi_prettyprint_status_register_bit(status, 4);
|
|
msg_cdbg("Chip status register: Bit 3 / Block Protect 1 (BP1) is "
|
|
"%sset\n", (status & (1 << 3)) ? "" : "not ");
|
|
msg_cdbg("Chip status register: Bit 2 / Block Protect 0 (BP0) is "
|
|
"%sset\n", (status & (1 << 2)) ? "" : "not ");
|
|
/* FIXME: Pretty-print detailed sector protection status. */
|
|
spi_prettyprint_status_register_welwip(status);
|
|
return 0;
|
|
}
|
|
|
|
int spi_prettyprint_status_register_at25fs040(struct flashctx *flash)
|
|
{
|
|
uint8_t status = spi_read_status_register(flash);
|
|
spi_prettyprint_status_register_hex(status);
|
|
|
|
spi_prettyprint_status_register_atmel_at25_wpen(status);
|
|
spi_prettyprint_status_register_bp(status, 4);
|
|
/* FIXME: Pretty-print detailed sector protection status. */
|
|
spi_prettyprint_status_register_welwip(status);
|
|
return 0;
|
|
}
|
|
|
|
int spi_prettyprint_status_register_at26df081a(struct flashctx *flash)
|
|
{
|
|
uint8_t status = spi_read_status_register(flash);
|
|
spi_prettyprint_status_register_hex(status);
|
|
|
|
spi_prettyprint_status_register_atmel_at25_srpl(status);
|
|
msg_cdbg("Chip status register: Sequential Program Mode Status (SPM) is %sset\n",
|
|
(status & (1 << 6)) ? "" : "not ");
|
|
spi_prettyprint_status_register_atmel_at25_epewpp(status);
|
|
spi_prettyprint_status_register_atmel_at25_swp(status);
|
|
spi_prettyprint_status_register_welwip(status);
|
|
return 0;
|
|
}
|
|
|
|
/* Some Atmel DataFlash chips support per sector protection bits and the write protection bits in the status
|
|
* register do indicate if none, some or all sectors are protected. It is possible to globally (un)lock all
|
|
* sectors at once by writing 0 not only the protection bits (2 and 3) but also completely unrelated bits (4 and
|
|
* 5) which normally are not touched.
|
|
* Affected are all known Atmel chips matched by AT2[56]D[FLQ]..1A? but the AT26DF041. */
|
|
int spi_disable_blockprotect_at2x_global_unprotect(struct flashctx *flash)
|
|
{
|
|
return spi_disable_blockprotect_generic(flash, 0x0C, 1 << 7, 1 << 4, 0x00);
|
|
}
|
|
|
|
int spi_disable_blockprotect_at2x_global_unprotect_sec(struct flashctx *flash)
|
|
{
|
|
/* FIXME: We should check the security lockdown. */
|
|
msg_cinfo("Ignoring security lockdown (if present)\n");
|
|
return spi_disable_blockprotect_at2x_global_unprotect(flash);
|
|
}
|
|
|
|
int spi_disable_blockprotect_at25f(struct flashctx *flash)
|
|
{
|
|
return spi_disable_blockprotect_generic(flash, 0x0C, 1 << 7, 0, 0xFF);
|
|
}
|
|
|
|
int spi_disable_blockprotect_at25f512a(struct flashctx *flash)
|
|
{
|
|
return spi_disable_blockprotect_generic(flash, 0x04, 1 << 7, 0, 0xFF);
|
|
}
|
|
|
|
int spi_disable_blockprotect_at25f512b(struct flashctx *flash)
|
|
{
|
|
return spi_disable_blockprotect_generic(flash, 0x04, 1 << 7, 1 << 4, 0xFF);
|
|
}
|
|
|
|
int spi_disable_blockprotect_at25fs010(struct flashctx *flash)
|
|
{
|
|
return spi_disable_blockprotect_generic(flash, 0x6C, 1 << 7, 0, 0xFF);
|
|
}
|
|
|
|
int spi_disable_blockprotect_at25fs040(struct flashctx *flash)
|
|
{
|
|
return spi_disable_blockprotect_generic(flash, 0x7C, 1 << 7, 0, 0xFF);
|
|
}
|
|
|
|
/* === Eon === */
|
|
|
|
int spi_prettyprint_status_register_en25s_wp(struct flashctx *flash)
|
|
{
|
|
uint8_t status = spi_read_status_register(flash);
|
|
spi_prettyprint_status_register_hex(status);
|
|
|
|
spi_prettyprint_status_register_srwd(status);
|
|
msg_cdbg("Chip status register: WP# disable (WPDIS) is %sabled\n", (status & (1 << 6)) ? "en " : "dis");
|
|
spi_prettyprint_status_register_bp(status, 3);
|
|
spi_prettyprint_status_register_welwip(status);
|
|
return 0;
|
|
}
|
|
|
|
/* === Intel/Numonyx/Micron - Spansion === */
|
|
|
|
int spi_disable_blockprotect_n25q(struct flashctx *flash)
|
|
{
|
|
return spi_disable_blockprotect_generic(flash, 0x5C, 1 << 7, 0, 0xFF);
|
|
}
|
|
|
|
int spi_prettyprint_status_register_n25q(struct flashctx *flash)
|
|
{
|
|
uint8_t status = spi_read_status_register(flash);
|
|
spi_prettyprint_status_register_hex(status);
|
|
|
|
spi_prettyprint_status_register_srwd(status);
|
|
if (flash->chip->total_size <= 32 / 8 * 1024) /* N25Q16 and N25Q32: reserved */
|
|
spi_prettyprint_status_register_bit(status, 6);
|
|
else
|
|
msg_cdbg("Chip status register: Block Protect 3 (BP3) is %sset\n",
|
|
(status & (1 << 6)) ? "" : "not ");
|
|
msg_cdbg("Chip status register: Top/Bottom (TB) is %s\n", (status & (1 << 5)) ? "bottom" : "top");
|
|
spi_prettyprint_status_register_bp(status, 2);
|
|
spi_prettyprint_status_register_welwip(status);
|
|
return 0;
|
|
}
|
|
|
|
/* Used by Intel/Numonyx S33 and Spansion S25FL-S chips */
|
|
/* TODO: Clear P_FAIL and E_FAIL with Clear SR Fail Flags Command (30h) here? */
|
|
int spi_disable_blockprotect_bp2_ep_srwd(struct flashctx *flash)
|
|
{
|
|
return spi_disable_blockprotect_bp2_srwd(flash);
|
|
}
|
|
|
|
/* Used by Intel/Numonyx S33 and Spansion S25FL-S chips */
|
|
int spi_prettyprint_status_register_bp2_ep_srwd(struct flashctx *flash)
|
|
{
|
|
uint8_t status = spi_read_status_register(flash);
|
|
spi_prettyprint_status_register_hex(status);
|
|
|
|
spi_prettyprint_status_register_srwd(status);
|
|
msg_cdbg("Chip status register: Program Fail Flag (P_FAIL) is %sset\n",
|
|
(status & (1 << 6)) ? "" : "not ");
|
|
msg_cdbg("Chip status register: Erase Fail Flag (E_FAIL) is %sset\n",
|
|
(status & (1 << 5)) ? "" : "not ");
|
|
spi_prettyprint_status_register_bp(status, 2);
|
|
spi_prettyprint_status_register_welwip(status);
|
|
return 0;
|
|
}
|
|
|
|
/* === SST === */
|
|
|
|
static void spi_prettyprint_status_register_sst25_common(uint8_t status)
|
|
{
|
|
spi_prettyprint_status_register_hex(status);
|
|
|
|
spi_prettyprint_status_register_bpl(status);
|
|
msg_cdbg("Chip status register: Auto Address Increment Programming (AAI) is %sset\n",
|
|
(status & (1 << 6)) ? "" : "not ");
|
|
spi_prettyprint_status_register_bp(status, 3);
|
|
spi_prettyprint_status_register_welwip(status);
|
|
}
|
|
|
|
int spi_prettyprint_status_register_sst25(struct flashctx *flash)
|
|
{
|
|
uint8_t status = spi_read_status_register(flash);
|
|
spi_prettyprint_status_register_sst25_common(status);
|
|
return 0;
|
|
}
|
|
|
|
int spi_prettyprint_status_register_sst25vf016(struct flashctx *flash)
|
|
{
|
|
static const char *const bpt[] = {
|
|
"none",
|
|
"1F0000H-1FFFFFH",
|
|
"1E0000H-1FFFFFH",
|
|
"1C0000H-1FFFFFH",
|
|
"180000H-1FFFFFH",
|
|
"100000H-1FFFFFH",
|
|
"all", "all"
|
|
};
|
|
uint8_t status = spi_read_status_register(flash);
|
|
spi_prettyprint_status_register_sst25_common(status);
|
|
msg_cdbg("Resulting block protection : %s\n", bpt[(status & 0x1c) >> 2]);
|
|
return 0;
|
|
}
|
|
|
|
int spi_prettyprint_status_register_sst25vf040b(struct flashctx *flash)
|
|
{
|
|
static const char *const bpt[] = {
|
|
"none",
|
|
"0x70000-0x7ffff",
|
|
"0x60000-0x7ffff",
|
|
"0x40000-0x7ffff",
|
|
"all blocks", "all blocks", "all blocks", "all blocks"
|
|
};
|
|
uint8_t status = spi_read_status_register(flash);
|
|
spi_prettyprint_status_register_sst25_common(status);
|
|
msg_cdbg("Resulting block protection : %s\n", bpt[(status & 0x1c) >> 2]);
|
|
return 0;
|
|
}
|