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8c3de01548
All these variables are only used in the files they are defined in, so they can be made static. (Backported as it untangles aliased global objects.) Change-Id: I1e55138adef540e9d3a2237aa5b289cb338c0608 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/flashrom/+/33747 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62612 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
194 lines
5.9 KiB
C
194 lines
5.9 KiB
C
/*
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* This file is part of the flashrom project.
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*
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* Copyright (C) 2010,2011 Carl-Daniel Hailfinger
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* Written by Carl-Daniel Hailfinger for Angelbird Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* Datasheets are not public (yet?) */
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#if defined(__i386__) || defined(__x86_64__)
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#include <stdlib.h>
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#include "flash.h"
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#include "programmer.h"
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#include "hwaccess.h"
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static uint8_t *mv_bar;
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static uint16_t mv_iobar;
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const struct dev_entry satas_mv[] = {
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/* 88SX6041 and 88SX6042 are the same according to the datasheet. */
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{0x11ab, 0x7042, OK, "Marvell", "88SX7042 PCI-e 4-port SATA-II"},
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{0},
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};
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#define NVRAM_PARAM 0x1045c
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#define FLASH_PARAM 0x1046c
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#define EXPANSION_ROM_BAR_CONTROL 0x00d2c
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#define PCI_BAR2_CONTROL 0x00c08
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#define GPIO_PORT_CONTROL 0x104f0
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static void satamv_chip_writeb(const struct flashctx *flash, uint8_t val,
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chipaddr addr);
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static uint8_t satamv_chip_readb(const struct flashctx *flash,
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const chipaddr addr);
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static const struct par_master par_master_satamv = {
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.chip_readb = satamv_chip_readb,
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.chip_readw = fallback_chip_readw,
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.chip_readl = fallback_chip_readl,
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.chip_readn = fallback_chip_readn,
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.chip_writeb = satamv_chip_writeb,
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.chip_writew = fallback_chip_writew,
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.chip_writel = fallback_chip_writel,
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.chip_writen = fallback_chip_writen,
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};
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/*
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* Random notes:
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* FCE# Flash Chip Enable
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* FWE# Flash Write Enable
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* FOE# Flash Output Enable
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* FALE[1:0] Flash Address Latch Enable
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* FAD[7:0] Flash Multiplexed Address/Data Bus
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* FA[2:0] Flash Address Low
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*
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* GPIO[15,2] GPIO Port Mode
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* GPIO[4:3] Flash Size
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*
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* 0xd2c Expansion ROM BAR Control
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* 0xc08 PCI BAR2 (Flash/NVRAM) Control
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* 0x1046c Flash Parameters
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*/
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int satamv_init(void)
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{
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struct pci_dev *dev = NULL;
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uintptr_t addr;
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uint32_t tmp;
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if (rget_io_perms())
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return 1;
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/* BAR0 has all internal registers memory mapped. */
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dev = pcidev_init(satas_mv, PCI_BASE_ADDRESS_0);
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if (!dev)
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return 1;
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addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0);
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if (!addr)
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return 1;
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mv_bar = rphysmap("Marvell 88SX7042 registers", addr, 0x20000);
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if (mv_bar == ERROR_PTR)
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return 1;
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tmp = pci_mmio_readl(mv_bar + FLASH_PARAM);
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msg_pspew("Flash Parameters:\n");
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msg_pspew("TurnOff=0x%01x\n", (tmp >> 0) & 0x7);
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msg_pspew("Acc2First=0x%01x\n", (tmp >> 3) & 0xf);
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msg_pspew("Acc2Next=0x%01x\n", (tmp >> 7) & 0xf);
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msg_pspew("ALE2Wr=0x%01x\n", (tmp >> 11) & 0x7);
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msg_pspew("WrLow=0x%01x\n", (tmp >> 14) & 0x7);
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msg_pspew("WrHigh=0x%01x\n", (tmp >> 17) & 0x7);
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msg_pspew("Reserved[21:20]=0x%01x\n", (tmp >> 20) & 0x3);
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msg_pspew("TurnOffExt=0x%01x\n", (tmp >> 22) & 0x1);
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msg_pspew("Acc2FirstExt=0x%01x\n", (tmp >> 23) & 0x1);
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msg_pspew("Acc2NextExt=0x%01x\n", (tmp >> 24) & 0x1);
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msg_pspew("ALE2WrExt=0x%01x\n", (tmp >> 25) & 0x1);
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msg_pspew("WrLowExt=0x%01x\n", (tmp >> 26) & 0x1);
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msg_pspew("WrHighExt=0x%01x\n", (tmp >> 27) & 0x1);
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msg_pspew("Reserved[31:28]=0x%01x\n", (tmp >> 28) & 0xf);
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tmp = pci_mmio_readl(mv_bar + EXPANSION_ROM_BAR_CONTROL);
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msg_pspew("Expansion ROM BAR Control:\n");
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msg_pspew("ExpROMSz=0x%01x\n", (tmp >> 19) & 0x7);
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/* Enable BAR2 mapping to flash */
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tmp = pci_mmio_readl(mv_bar + PCI_BAR2_CONTROL);
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msg_pspew("PCI BAR2 (Flash/NVRAM) Control:\n");
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msg_pspew("Bar2En=0x%01x\n", (tmp >> 0) & 0x1);
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msg_pspew("BAR2TransAttr=0x%01x\n", (tmp >> 1) & 0x1f);
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msg_pspew("BAR2Sz=0x%01x\n", (tmp >> 19) & 0x7);
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tmp &= 0xffffffc0;
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tmp |= 0x0000001f;
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pci_rmmio_writel(tmp, mv_bar + PCI_BAR2_CONTROL);
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/* Enable flash: GPIO Port Control Register 0x104f0 */
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tmp = pci_mmio_readl(mv_bar + GPIO_PORT_CONTROL);
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msg_pspew("GPIOPortMode=0x%01x\n", (tmp >> 0) & 0x3);
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if (((tmp >> 0) & 0x3) != 0x2)
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msg_pinfo("Warning! Either the straps are incorrect or you "
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"have no flash or someone overwrote the strap "
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"values!\n");
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tmp &= 0xfffffffc;
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tmp |= 0x2;
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pci_rmmio_writel(tmp, mv_bar + GPIO_PORT_CONTROL);
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/* Get I/O BAR location. */
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addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_2);
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if (!addr)
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return 1;
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/* Truncate to reachable range.
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* FIXME: Check if the I/O BAR is actually reachable.
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* This is an arch specific check.
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*/
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mv_iobar = addr & 0xffff;
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msg_pspew("Activating I/O BAR at 0x%04x\n", mv_iobar);
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/* 512 kByte with two 8-bit latches, and
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* 4 MByte with additional 3-bit latch. */
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max_rom_decode.parallel = 4 * 1024 * 1024;
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register_par_master(&par_master_satamv, BUS_PARALLEL);
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return 0;
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}
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/* BAR2 (MEM) can map NVRAM and flash. We set it to flash in the init function.
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* If BAR2 is disabled, it still can be accessed indirectly via BAR1 (I/O).
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* This code only supports indirect accesses for now.
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*/
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/* Indirect access to via the I/O BAR1. */
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static void satamv_indirect_chip_writeb(uint8_t val, chipaddr addr)
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{
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/* 0x80000000 selects BAR2 for remapping. */
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OUTL(((uint32_t)addr | 0x80000000) & 0xfffffffc, mv_iobar);
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OUTB(val, mv_iobar + 0x80 + (addr & 0x3));
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}
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/* Indirect access to via the I/O BAR1. */
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static uint8_t satamv_indirect_chip_readb(const chipaddr addr)
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{
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/* 0x80000000 selects BAR2 for remapping. */
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OUTL(((uint32_t)addr | 0x80000000) & 0xfffffffc, mv_iobar);
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return INB(mv_iobar + 0x80 + (addr & 0x3));
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}
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/* FIXME: Prefer direct access to BAR2 if BAR2 is active. */
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static void satamv_chip_writeb(const struct flashctx *flash, uint8_t val,
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chipaddr addr)
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{
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satamv_indirect_chip_writeb(val, addr);
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}
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/* FIXME: Prefer direct access to BAR2 if BAR2 is active. */
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static uint8_t satamv_chip_readb(const struct flashctx *flash,
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const chipaddr addr)
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{
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return satamv_indirect_chip_readb(addr);
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}
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#else
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#error PCI port I/O access is not supported on this architecture yet.
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#endif
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