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5643c0782e
Convert chips to block_erasers: ST_M25PE10 ST_M25PE20 ST_M25PE40 ST_M25PE80 ST_M25PE16 PMC_25LV010 PMC_25LV016B PMC_25LV020 PMC_25LV040 PMC_25LV080B PMC_25LV512 PMC_39F010 PMC_49FL002 PMC_49FL004 SANYO_LE25FW203A SPANSION_S25FL016A Added spi_block_erase_d7 for PMC chips. Corresponding to flashrom svn r867. Signed-off-by: Sean Nelson <audiohacked@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
120 lines
3.2 KiB
C
120 lines
3.2 KiB
C
/*
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* This file is part of the flashrom project.
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*
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* Copyright (C) 2007, 2008 Carl-Daniel Hailfinger
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef __SPI_H__
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#define __SPI_H__ 1
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/*
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* Contains the generic SPI headers
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*/
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/* Read Electronic ID */
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#define JEDEC_RDID 0x9f
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#define JEDEC_RDID_OUTSIZE 0x01
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#define JEDEC_RDID_INSIZE 0x03
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/* AT25F512A has bit 3 as don't care bit in commands */
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#define AT25F512A_RDID 0x15
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#define AT25F512A_RDID_OUTSIZE 0x01
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#define AT25F512A_RDID_INSIZE 0x02
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/* Read Electronic Manufacturer Signature */
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#define JEDEC_REMS 0x90
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#define JEDEC_REMS_OUTSIZE 0x04
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#define JEDEC_REMS_INSIZE 0x02
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/* Read Electronic Signature */
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#define JEDEC_RES 0xab
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#define JEDEC_RES_OUTSIZE 0x04
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#define JEDEC_RES_INSIZE 0x01
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/* Write Enable */
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#define JEDEC_WREN 0x06
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#define JEDEC_WREN_OUTSIZE 0x01
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#define JEDEC_WREN_INSIZE 0x00
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/* Write Disable */
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#define JEDEC_WRDI 0x04
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#define JEDEC_WRDI_OUTSIZE 0x01
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#define JEDEC_WRDI_INSIZE 0x00
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/* Chip Erase 0x60 is supported by Macronix/SST chips. */
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#define JEDEC_CE_60 0x60
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#define JEDEC_CE_60_OUTSIZE 0x01
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#define JEDEC_CE_60_INSIZE 0x00
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/* Chip Erase 0xc7 is supported by SST/ST/EON/Macronix chips. */
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#define JEDEC_CE_C7 0xc7
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#define JEDEC_CE_C7_OUTSIZE 0x01
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#define JEDEC_CE_C7_INSIZE 0x00
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/* Block Erase 0x52 is supported by SST and old Atmel chips. */
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#define JEDEC_BE_52 0x52
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#define JEDEC_BE_52_OUTSIZE 0x04
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#define JEDEC_BE_52_INSIZE 0x00
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/* Block Erase 0xd8 is supported by EON/Macronix chips. */
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#define JEDEC_BE_D8 0xd8
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#define JEDEC_BE_D8_OUTSIZE 0x04
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#define JEDEC_BE_D8_INSIZE 0x00
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/* Block Erase 0xd7 is supported by PMC chips. */
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#define JEDEC_BE_D7 0xd7
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#define JEDEC_BE_D7_OUTSIZE 0x04
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#define JEDEC_BE_D7_INSIZE 0x00
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/* Sector Erase 0x20 is supported by Macronix/SST chips. */
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#define JEDEC_SE 0x20
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#define JEDEC_SE_OUTSIZE 0x04
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#define JEDEC_SE_INSIZE 0x00
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/* Read Status Register */
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#define JEDEC_RDSR 0x05
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#define JEDEC_RDSR_OUTSIZE 0x01
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#define JEDEC_RDSR_INSIZE 0x01
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#define JEDEC_RDSR_BIT_WIP (0x01 << 0)
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/* Write Status Enable */
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#define JEDEC_EWSR 0x50
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#define JEDEC_EWSR_OUTSIZE 0x01
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#define JEDEC_EWSR_INSIZE 0x00
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/* Write Status Register */
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#define JEDEC_WRSR 0x01
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#define JEDEC_WRSR_OUTSIZE 0x02
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#define JEDEC_WRSR_INSIZE 0x00
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/* Read the memory */
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#define JEDEC_READ 0x03
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#define JEDEC_READ_OUTSIZE 0x04
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/* JEDEC_READ_INSIZE : any length */
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/* Write memory byte */
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#define JEDEC_BYTE_PROGRAM 0x02
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#define JEDEC_BYTE_PROGRAM_OUTSIZE 0x05
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#define JEDEC_BYTE_PROGRAM_INSIZE 0x00
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/* Error codes */
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#define SPI_GENERIC_ERROR -1
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#define SPI_INVALID_OPCODE -2
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#define SPI_INVALID_ADDRESS -3
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#define SPI_INVALID_LENGTH -4
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#endif /* !__SPI_H__ */
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