mirror of
https://review.coreboot.org/flashrom.git
synced 2025-04-29 16:03:47 +02:00
5820f42ef2
Use chipaddr instead of volatile uint8_t * because when we access chips
in external flashers, they are not accessed via pointers at all.
Benefits: This allows us to differentiate between volatile machine
memory accesses and flash chip accesses. It also enforces usage
of chip_{read,write}[bwl] to access flash chips, so nobody will
unintentionally use pointers to access chips anymore. Some unneeded
casts are removed as well. Grepping for chip operations and machine
memory operations doesn't yield any false positives anymore.
Compile tested on 32 bit and 64 bit Linux.
Corresponding to flashrom svn r519.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
125 lines
3.1 KiB
C
125 lines
3.1 KiB
C
/*
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* This file is part of the flashrom project.
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*
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* Copyright (C) 2007 Carl-Daniel Hailfinger
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/*
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* EN29F512 has 1C,21
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* EN29F010 has 1C,20
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* EN29F040A has 1C,04
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* EN29LV010 has 1C,6E and uses short F0 reset sequence
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* EN29LV040(A) has 1C,4F and uses short F0 reset sequence
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*/
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#include <stdio.h>
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#include <stdint.h>
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#include "flash.h"
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int probe_en29f512(struct flashchip *flash)
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{
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chipaddr bios = flash->virtual_memory;
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uint8_t id1, id2;
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chip_writeb(0xAA, bios + 0x555);
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chip_writeb(0x55, bios + 0x2AA);
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chip_writeb(0x90, bios + 0x555);
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myusec_delay(10);
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id1 = chip_readb(bios + 0x100);
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id2 = chip_readb(bios + 0x101);
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/* exit by writing F0 anywhere? or the code below */
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chip_writeb(0xAA, bios + 0x555);
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chip_writeb(0x55, bios + 0x2AA);
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chip_writeb(0xF0, bios + 0x555);
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printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, id1, id2);
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if (id1 == flash->manufacture_id && id2 == flash->model_id)
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return 1;
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return 0;
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}
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/*
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* EN29F002AT has 1C,92
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* EN29F002AB has 1C,97
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*/
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/* This does not seem to function properly for EN29F002NT. */
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int probe_en29f002a(struct flashchip *flash)
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{
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chipaddr bios = flash->virtual_memory;
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uint8_t id1, id2;
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chip_writeb(0xAA, bios + 0x555);
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chip_writeb(0x55, bios + 0xAAA);
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chip_writeb(0x90, bios + 0x555);
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myusec_delay(10);
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id1 = chip_readb(bios + 0x100);
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id2 = chip_readb(bios + 0x101);
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/* exit by writing F0 anywhere? or the code below */
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chip_writeb(0xAA, bios + 0x555);
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chip_writeb(0x55, bios + 0xAAA);
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chip_writeb(0xF0, bios + 0x555);
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printf_debug("%s: id1 0x%x, id2 0x%x\n", __FUNCTION__, id1, id2);
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if (id1 == flash->manufacture_id && id2 == flash->model_id)
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return 1;
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return 0;
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}
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/* The EN29F002 chip needs repeated single byte writing, no block writing. */
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int write_en29f002a(struct flashchip *flash, uint8_t *buf)
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{
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int i;
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int total_size = flash->total_size * 1024;
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chipaddr bios = flash->virtual_memory;
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chipaddr dst = bios;
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//chip_writeb(0xF0, bios);
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myusec_delay(10);
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erase_chip_jedec(flash);
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printf("Programming page: ");
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for (i = 0; i < total_size; i++) {
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/* write to the sector */
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if ((i & 0xfff) == 0)
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printf("address: 0x%08lx", (unsigned long)i);
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chip_writeb(0xAA, bios + 0x5555);
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chip_writeb(0x55, bios + 0x2AAA);
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chip_writeb(0xA0, bios + 0x5555);
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chip_writeb(*buf++, dst++);
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/* wait for Toggle bit ready */
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toggle_ready_jedec(dst);
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if ((i & 0xfff) == 0)
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printf("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b");
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}
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printf("\n");
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return 0;
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}
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