mirror of
https://review.coreboot.org/flashrom.git
synced 2025-04-27 15:12:36 +02:00
5820f42ef2
Use chipaddr instead of volatile uint8_t * because when we access chips
in external flashers, they are not accessed via pointers at all.
Benefits: This allows us to differentiate between volatile machine
memory accesses and flash chip accesses. It also enforces usage
of chip_{read,write}[bwl] to access flash chips, so nobody will
unintentionally use pointers to access chips anymore. Some unneeded
casts are removed as well. Grepping for chip operations and machine
memory operations doesn't yield any false positives anymore.
Compile tested on 32 bit and 64 bit Linux.
Corresponding to flashrom svn r519.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
105 lines
2.8 KiB
C
105 lines
2.8 KiB
C
/*
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* This file is part of the flashrom project.
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*
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* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <stdlib.h>
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#include <string.h>
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#include <fcntl.h>
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#include <sys/types.h>
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#include <sys/stat.h>
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#include <errno.h>
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#include "flash.h"
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#define BIOS_ROM_ADDR 0x04
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#define BIOS_ROM_DATA 0x08
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#define INT_STATUS 0x0e
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#define SELECT_REG_WINDOW 0x800
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#define PCI_VENDOR_ID_3COM 0x10b7
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struct pcidev_status nics_3com[] = {
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/* 3C90xB */
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{0x10b7, 0x9055, PCI_NT, "3COM", "3C90xB: PCI 10/100 Mbps; shared 10BASE-T/100BASE-TX"},
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{0x10b7, 0x9001, PCI_NT, "3COM", "3C90xB: PCI 10/100 Mbps; shared 10BASE-T/100BASE-T4" },
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{0x10b7, 0x9004, PCI_NT, "3COM", "3C90xB: PCI 10BASE-T (TPO)" },
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{0x10b7, 0x9005, PCI_NT, "3COM", "3C90xB: PCI 10BASE-T/10BASE2/AUI (COMBO)" },
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{0x10b7, 0x9006, PCI_NT, "3COM", "3C90xB: PCI 10BASE-T/10BASE2 (TPC)" },
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{0x10b7, 0x900a, PCI_NT, "3COM", "3C90xB: PCI 10BASE-FL" },
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{0x10b7, 0x905a, PCI_NT, "3COM", "3C90xB: PCI 10BASE-FX" },
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/* 3C905C */
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{0x10b7, 0x9200, PCI_OK, "3COM", "3C905C: EtherLink 10/100 PCI (TX)" },
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/* 3C980C */
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{0x10b7, 0x9805, PCI_NT, "3COM", "3C980C: EtherLink Server 10/100 PCI (TX)" },
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{},
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};
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int nic3com_init(void)
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{
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get_io_perms();
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io_base_addr = pcidev_init(PCI_VENDOR_ID_3COM, nics_3com);
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/*
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* The lowest 16 bytes of the I/O mapped register space of (most) 3COM
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* cards form a 'register window' into one of multiple (usually 8)
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* register banks. For 3C90xB/3C90xC we need register window/bank 0.
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*/
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OUTW(SELECT_REG_WINDOW + 0, io_base_addr + INT_STATUS);
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return 0;
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}
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int nic3com_shutdown(void)
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{
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free(pcidev_bdf);
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pci_cleanup(pacc);
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#if defined(__FreeBSD__) || defined(__DragonFly__)
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close(io_fd);
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#endif
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return 0;
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}
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void *nic3com_map(const char *descr, unsigned long phys_addr, size_t len)
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{
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return 0;
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}
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void nic3com_unmap(void *virt_addr, size_t len)
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{
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}
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void nic3com_chip_writeb(uint8_t val, chipaddr addr)
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{
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OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR);
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OUTB(val, io_base_addr + BIOS_ROM_DATA);
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}
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uint8_t nic3com_chip_readb(const chipaddr addr)
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{
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uint8_t val;
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OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR);
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val = INB(io_base_addr + BIOS_ROM_DATA);
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return val;
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}
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