mirror of
https://review.coreboot.org/flashrom.git
synced 2025-04-27 07:02:34 +02:00
5b997c3ed6
Programmer specific functions are of absolutely no interest to any file except those dealing with programmer specific actions (special SPI commands and the generic core). The new header structure is as follows (and yes, improvements are possible): flashchips.h flash chip IDs chipdrivers.h chip-specific read/write/... functions flash.h common header for all stuff that doesn't fit elsewhere hwaccess.h hardware access functions programmer.h programmer specific functions coreboot_tables.h header from coreboot, internal programmer only spi.h SPI command definitions Corresponding to flashrom svn r1112. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
80 lines
2.1 KiB
C
80 lines
2.1 KiB
C
/*
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* This file is part of the flashrom project.
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*
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* Copyright (C) 2009 Joerg Fischer <turboj@web.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <stdlib.h>
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#include "flash.h"
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#include "programmer.h"
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#define PCI_VENDOR_ID_DRKAISER 0x1803
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#define PCI_MAGIC_DRKAISER_ADDR 0x50
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#define PCI_MAGIC_DRKAISER_VALUE 0xa971
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/* Mask to restrict flash accesses to the 128kB memory window. */
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#define DRKAISER_MEMMAP_MASK ((1 << 17) - 1)
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const struct pcidev_status drkaiser_pcidev[] = {
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{0x1803, 0x5057, OK, "Dr. Kaiser", "PC-Waechter (Actel FPGA)"},
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{},
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};
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static uint8_t *drkaiser_bar;
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int drkaiser_init(void)
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{
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uint32_t addr;
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get_io_perms();
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addr = pcidev_init(PCI_VENDOR_ID_DRKAISER, PCI_BASE_ADDRESS_2,
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drkaiser_pcidev);
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/* Write magic register to enable flash write. */
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pci_write_word(pcidev_dev, PCI_MAGIC_DRKAISER_ADDR,
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PCI_MAGIC_DRKAISER_VALUE);
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/* Map 128KB flash memory window. */
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drkaiser_bar = physmap("Dr. Kaiser PC-Waechter flash memory",
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addr, 128 * 1024);
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buses_supported = CHIP_BUSTYPE_PARALLEL;
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return 0;
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}
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int drkaiser_shutdown(void)
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{
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/* Write protect the flash again. */
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pci_write_word(pcidev_dev, PCI_MAGIC_DRKAISER_ADDR, 0);
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pci_cleanup(pacc);
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release_io_perms();
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return 0;
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};
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void drkaiser_chip_writeb(uint8_t val, chipaddr addr)
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{
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pci_mmio_writeb(val, drkaiser_bar + (addr & DRKAISER_MEMMAP_MASK));
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}
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uint8_t drkaiser_chip_readb(const chipaddr addr)
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{
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return pci_mmio_readb(drkaiser_bar + (addr & DRKAISER_MEMMAP_MASK));
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}
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