mirror of
https://review.coreboot.org/flashrom.git
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5b997c3ed6
Programmer specific functions are of absolutely no interest to any file except those dealing with programmer specific actions (special SPI commands and the generic core). The new header structure is as follows (and yes, improvements are possible): flashchips.h flash chip IDs chipdrivers.h chip-specific read/write/... functions flash.h common header for all stuff that doesn't fit elsewhere hwaccess.h hardware access functions programmer.h programmer specific functions coreboot_tables.h header from coreboot, internal programmer only spi.h SPI command definitions Corresponding to flashrom svn r1112. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
124 lines
3.3 KiB
C
124 lines
3.3 KiB
C
/*
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* This file is part of the flashrom project.
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*
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* Copyright (C) 2009,2010 Carl-Daniel Hailfinger
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/* Driver for the SPIPGM hardware by "RayeR" Martin Rehak.
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* See http://rayer.ic.cz/elektro/spipgm.htm for schematics and instructions.
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*/
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/* This driver uses non-portable direct I/O port accesses which won't work on
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* any non-x86 platform, and even on x86 there is a high chance there will be
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* collisions with any loaded parallel port drivers.
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* The big advantage of direct port I/O is OS independence and speed because
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* most OS parport drivers will perform many unnecessary accesses although
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* this driver just treats the parallel port as a GPIO set.
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*/
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#if defined(__i386__) || defined(__x86_64__)
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#include "flash.h"
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#include "programmer.h"
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/* We have two sets of pins, out and in. The numbers for both sets are
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* independent and are bitshift values, not real pin numbers.
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*/
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/* Pins for master->slave direction */
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#define SPI_CS_PIN 5
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#define SPI_SCK_PIN 6
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#define SPI_MOSI_PIN 7
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/* Pins for slave->master direction */
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#define SPI_MISO_PIN 6
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static int lpt_iobase;
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/* FIXME: All rayer_bitbang_set_* functions could use caching of the value
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* stored at port lpt_iobase to avoid unnecessary INB. In theory, only one
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* INB(lpt_iobase) would be needed on programmer init to get the initial
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* value.
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*/
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void rayer_bitbang_set_cs(int val)
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{
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uint8_t tmp;
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tmp = INB(lpt_iobase);
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tmp &= ~(1 << SPI_CS_PIN);
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tmp |= (val << SPI_CS_PIN);
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OUTB(tmp, lpt_iobase);
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}
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void rayer_bitbang_set_sck(int val)
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{
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uint8_t tmp;
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tmp = INB(lpt_iobase);
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tmp &= ~(1 << SPI_SCK_PIN);
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tmp |= (val << SPI_SCK_PIN);
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OUTB(tmp, lpt_iobase);
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}
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void rayer_bitbang_set_mosi(int val)
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{
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uint8_t tmp;
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tmp = INB(lpt_iobase);
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tmp &= ~(1 << SPI_MOSI_PIN);
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tmp |= (val << SPI_MOSI_PIN);
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OUTB(tmp, lpt_iobase);
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}
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int rayer_bitbang_get_miso(void)
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{
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uint8_t tmp;
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tmp = INB(lpt_iobase + 1);
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tmp = (tmp >> SPI_MISO_PIN) & 0x1;
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return tmp;
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}
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static const struct bitbang_spi_master bitbang_spi_master_rayer = {
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.type = BITBANG_SPI_MASTER_RAYER,
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.set_cs = rayer_bitbang_set_cs,
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.set_sck = rayer_bitbang_set_sck,
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.set_mosi = rayer_bitbang_set_mosi,
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.get_miso = rayer_bitbang_get_miso,
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};
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int rayer_spi_init(void)
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{
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/* Pick a default value for now. */
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lpt_iobase = 0x378;
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msg_pdbg("Using port 0x%x as I/O base for parallel port access.\n",
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lpt_iobase);
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get_io_perms();
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/* 1 usec halfperiod delay for now. */
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if (bitbang_spi_init(&bitbang_spi_master_rayer, 1))
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return 1;
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buses_supported = CHIP_BUSTYPE_SPI;
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spi_controller = SPI_CONTROLLER_RAYER;
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return 0;
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}
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#else
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#error PCI port I/O access is not supported on this architecture yet.
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#endif
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