mirror of
https://review.coreboot.org/flashrom.git
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5b997c3ed6
Programmer specific functions are of absolutely no interest to any file except those dealing with programmer specific actions (special SPI commands and the generic core). The new header structure is as follows (and yes, improvements are possible): flashchips.h flash chip IDs chipdrivers.h chip-specific read/write/... functions flash.h common header for all stuff that doesn't fit elsewhere hwaccess.h hardware access functions programmer.h programmer specific functions coreboot_tables.h header from coreboot, internal programmer only spi.h SPI command definitions Corresponding to flashrom svn r1112. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
113 lines
3.2 KiB
C
113 lines
3.2 KiB
C
/*
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* This file is part of the flashrom project.
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*
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* Copyright (C) 2009 Rudolf Marek <r.marek@assembler.cz>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/* Datasheets can be found on http://www.siliconimage.com. Great thanks! */
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#include <stdlib.h>
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#include "flash.h"
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#include "programmer.h"
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#define PCI_VENDOR_ID_SII 0x1095
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uint8_t *sii_bar;
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static uint16_t id;
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const struct pcidev_status satas_sii[] = {
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{0x1095, 0x0680, OK, "Silicon Image", "PCI0680 Ultra ATA-133 Host Ctrl"},
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{0x1095, 0x3112, OK, "Silicon Image", "SiI 3112 [SATALink/SATARaid] SATA Ctrl"},
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{0x1095, 0x3114, OK, "Silicon Image", "SiI 3114 [SATALink/SATARaid] SATA Ctrl"},
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{0x1095, 0x3124, NT, "Silicon Image", "SiI 3124 PCI-X SATA Ctrl"},
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{0x1095, 0x3132, OK, "Silicon Image", "SiI 3132 SATA Raid II Ctrl"},
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{0x1095, 0x3512, NT, "Silicon Image", "SiI 3512 [SATALink/SATARaid] SATA Ctrl"},
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{},
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};
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int satasii_init(void)
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{
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uint32_t addr;
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uint16_t reg_offset;
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get_io_perms();
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pcidev_init(PCI_VENDOR_ID_SII, PCI_BASE_ADDRESS_0, satas_sii);
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id = pcidev_dev->device_id;
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if ((id == 0x3132) || (id == 0x3124)) {
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addr = pci_read_long(pcidev_dev, PCI_BASE_ADDRESS_0) & ~0x07;
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reg_offset = 0x70;
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} else {
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addr = pci_read_long(pcidev_dev, PCI_BASE_ADDRESS_5) & ~0x07;
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reg_offset = 0x50;
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}
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sii_bar = physmap("SATA SIL registers", addr, 0x100) + reg_offset;
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/* Check if ROM cycle are OK. */
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if ((id != 0x0680) && (!(pci_mmio_readl(sii_bar) & (1 << 26))))
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msg_pinfo("Warning: Flash seems unconnected.\n");
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buses_supported = CHIP_BUSTYPE_PARALLEL;
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return 0;
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}
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int satasii_shutdown(void)
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{
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pci_cleanup(pacc);
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release_io_perms();
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return 0;
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}
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void satasii_chip_writeb(uint8_t val, chipaddr addr)
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{
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uint32_t ctrl_reg, data_reg;
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while ((ctrl_reg = pci_mmio_readl(sii_bar)) & (1 << 25)) ;
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/* Mask out unused/reserved bits, set writes and start transaction. */
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ctrl_reg &= 0xfcf80000;
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ctrl_reg |= (1 << 25) | (0 << 24) | ((uint32_t) addr & 0x7ffff);
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data_reg = (pci_mmio_readl((sii_bar + 4)) & ~0xff) | val;
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pci_mmio_writel(data_reg, (sii_bar + 4));
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pci_mmio_writel(ctrl_reg, sii_bar);
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while (pci_mmio_readl(sii_bar) & (1 << 25)) ;
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}
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uint8_t satasii_chip_readb(const chipaddr addr)
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{
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uint32_t ctrl_reg;
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while ((ctrl_reg = pci_mmio_readl(sii_bar)) & (1 << 25)) ;
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/* Mask out unused/reserved bits, set reads and start transaction. */
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ctrl_reg &= 0xfcf80000;
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ctrl_reg |= (1 << 25) | (1 << 24) | ((uint32_t) addr & 0x7ffff);
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pci_mmio_writel(ctrl_reg, sii_bar);
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while (pci_mmio_readl(sii_bar) & (1 << 25)) ;
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return (pci_mmio_readl(sii_bar + 4)) & 0xff;
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}
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