mirror of
https://review.coreboot.org/flashrom.git
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d6bb828b01
Get_io_perms() is renamed to rget_io_perms() and automatically registers a function to release I/O permissions on shutdown. Actually release I/O permissions on Solaris and iopl()-supporting operating systems like Linux. This patch fixes quite a few programmers which forgot to release I/O permissions on shutdown, and it simplifies the shutdown and error handling code for all others. Do not call exit(1) if I/O permissions are denied and return an error instead. This part of the patch was written by Niklas Söderlund. Corresponding to flashrom svn r1551. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Signed-off-by: Niklas Söderlund <niso@kth.se> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
115 lines
3.7 KiB
C
115 lines
3.7 KiB
C
/*
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* This file is part of the flashrom project.
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*
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* Copyright (C) 2010 Andrew Morgan <ziltro@ziltro.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#if defined(__i386__) || defined(__x86_64__)
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#include <stdlib.h>
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#include "flash.h"
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#include "programmer.h"
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#include "hwaccess.h"
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#define PCI_VENDOR_ID_NATSEMI 0x100b
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#define BOOT_ROM_ADDR 0x50
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#define BOOT_ROM_DATA 0x54
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const struct pcidev_status nics_natsemi[] = {
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{0x100b, 0x0020, NT, "National Semiconductor", "DP83815/DP83816"},
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{0x100b, 0x0022, NT, "National Semiconductor", "DP83820"},
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{},
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};
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static void nicnatsemi_chip_writeb(const struct flashctx *flash, uint8_t val,
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chipaddr addr);
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static uint8_t nicnatsemi_chip_readb(const struct flashctx *flash,
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const chipaddr addr);
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static const struct par_programmer par_programmer_nicnatsemi = {
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.chip_readb = nicnatsemi_chip_readb,
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.chip_readw = fallback_chip_readw,
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.chip_readl = fallback_chip_readl,
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.chip_readn = fallback_chip_readn,
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.chip_writeb = nicnatsemi_chip_writeb,
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.chip_writew = fallback_chip_writew,
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.chip_writel = fallback_chip_writel,
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.chip_writen = fallback_chip_writen,
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};
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static int nicnatsemi_shutdown(void *data)
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{
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pci_cleanup(pacc);
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return 0;
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}
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int nicnatsemi_init(void)
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{
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if (rget_io_perms())
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return 1;
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io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_natsemi);
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if (register_shutdown(nicnatsemi_shutdown, NULL))
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return 1;
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/* The datasheet shows address lines MA0-MA16 in one place and MA0-MA15
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* in another. My NIC has MA16 connected to A16 on the boot ROM socket
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* so I'm assuming it is accessible. If not then next line wants to be
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* max_rom_decode.parallel = 65536; and the mask in the read/write
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* functions below wants to be 0x0000FFFF.
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*/
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max_rom_decode.parallel = 131072;
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register_par_programmer(&par_programmer_nicnatsemi, BUS_PARALLEL);
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return 0;
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}
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static void nicnatsemi_chip_writeb(const struct flashctx *flash, uint8_t val,
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chipaddr addr)
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{
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OUTL((uint32_t)addr & 0x0001FFFF, io_base_addr + BOOT_ROM_ADDR);
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/*
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* The datasheet requires 32 bit accesses to this register, but it seems
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* that requirement might only apply if the register is memory mapped.
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* Bits 8-31 of this register are apparently don't care, and if this
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* register is I/O port mapped, 8 bit accesses to the lowest byte of the
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* register seem to work fine. Due to that, we ignore the advice in the
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* data sheet.
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*/
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OUTB(val, io_base_addr + BOOT_ROM_DATA);
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}
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static uint8_t nicnatsemi_chip_readb(const struct flashctx *flash,
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const chipaddr addr)
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{
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OUTL(((uint32_t)addr & 0x0001FFFF), io_base_addr + BOOT_ROM_ADDR);
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/*
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* The datasheet requires 32 bit accesses to this register, but it seems
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* that requirement might only apply if the register is memory mapped.
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* Bits 8-31 of this register are apparently don't care, and if this
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* register is I/O port mapped, 8 bit accesses to the lowest byte of the
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* register seem to work fine. Due to that, we ignore the advice in the
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* data sheet.
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*/
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return INB(io_base_addr + BOOT_ROM_DATA);
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}
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#else
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#error PCI port I/O access is not supported on this architecture yet.
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#endif
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