mirror of
https://review.coreboot.org/flashrom.git
synced 2025-04-26 22:52:34 +02:00
67d5015617
Drop the explicit need to specify the default 'fallback_{un}map'
callback function pointer from the 'programmer_entry' struct.
This is a reasonable default for every other driver in the tree
with only a select few exceptions [atavia, serprog, dummyflasher
and internal].
Thus this simplifies driver development and paves way
to remove the 'programmer' global handle.
Change-Id: I5ea7bd68f7ae2cd4af9902ef07255ab6ce0bfdb3
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/67404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
131 lines
3.9 KiB
C
131 lines
3.9 KiB
C
/*
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* This file is part of the flashrom project.
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*
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* Copyright (C) 2010 Andrew Morgan <ziltro@ziltro.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <stdlib.h>
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#include "flash.h"
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#include "programmer.h"
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#include "hwaccess_x86_io.h"
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#include "platform/pci.h"
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#define PCI_VENDOR_ID_NATSEMI 0x100b
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#define BOOT_ROM_ADDR 0x50
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#define BOOT_ROM_DATA 0x54
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struct nicnatsemi_data {
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uint32_t io_base_addr;
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};
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static const struct dev_entry nics_natsemi[] = {
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{0x100b, 0x0020, NT, "National Semiconductor", "DP83815/DP83816"},
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{0x100b, 0x0022, NT, "National Semiconductor", "DP83820"},
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{0},
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};
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static void nicnatsemi_chip_writeb(const struct flashctx *flash, uint8_t val,
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chipaddr addr)
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{
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const struct nicnatsemi_data *data = flash->mst->par.data;
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OUTL((uint32_t)addr & 0x0001FFFF, data->io_base_addr + BOOT_ROM_ADDR);
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/*
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* The datasheet requires 32 bit accesses to this register, but it seems
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* that requirement might only apply if the register is memory mapped.
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* Bits 8-31 of this register are apparently don't care, and if this
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* register is I/O port mapped, 8 bit accesses to the lowest byte of the
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* register seem to work fine. Due to that, we ignore the advice in the
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* data sheet.
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*/
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OUTB(val, data->io_base_addr + BOOT_ROM_DATA);
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}
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static uint8_t nicnatsemi_chip_readb(const struct flashctx *flash,
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const chipaddr addr)
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{
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const struct nicnatsemi_data *data = flash->mst->par.data;
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OUTL(((uint32_t)addr & 0x0001FFFF), data->io_base_addr + BOOT_ROM_ADDR);
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/*
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* The datasheet requires 32 bit accesses to this register, but it seems
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* that requirement might only apply if the register is memory mapped.
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* Bits 8-31 of this register are apparently don't care, and if this
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* register is I/O port mapped, 8 bit accesses to the lowest byte of the
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* register seem to work fine. Due to that, we ignore the advice in the
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* data sheet.
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*/
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return INB(data->io_base_addr + BOOT_ROM_DATA);
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}
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static int nicnatsemi_shutdown(void *par_data)
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{
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free(par_data);
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return 0;
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}
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static const struct par_master par_master_nicnatsemi = {
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.chip_readb = nicnatsemi_chip_readb,
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.chip_readw = fallback_chip_readw,
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.chip_readl = fallback_chip_readl,
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.chip_readn = fallback_chip_readn,
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.chip_writeb = nicnatsemi_chip_writeb,
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.chip_writew = fallback_chip_writew,
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.chip_writel = fallback_chip_writel,
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.chip_writen = fallback_chip_writen,
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.shutdown = nicnatsemi_shutdown,
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};
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static int nicnatsemi_init(const struct programmer_cfg *cfg)
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{
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struct pci_dev *dev = NULL;
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uint32_t io_base_addr;
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if (rget_io_perms())
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return 1;
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dev = pcidev_init(cfg, nics_natsemi, PCI_BASE_ADDRESS_0);
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if (!dev)
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return 1;
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io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0);
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if (!io_base_addr)
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return 1;
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struct nicnatsemi_data *data = calloc(1, sizeof(*data));
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if (!data) {
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msg_perr("Unable to allocate space for PAR master data\n");
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return 1;
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}
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data->io_base_addr = io_base_addr;
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/* The datasheet shows address lines MA0-MA16 in one place and MA0-MA15
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* in another. My NIC has MA16 connected to A16 on the boot ROM socket
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* so I'm assuming it is accessible. If not then next line wants to be
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* max_rom_decode.parallel = 65536; and the mask in the read/write
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* functions below wants to be 0x0000FFFF.
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*/
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max_rom_decode.parallel = 131072;
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return register_par_master(&par_master_nicnatsemi, BUS_PARALLEL, data);
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}
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const struct programmer_entry programmer_nicnatsemi = {
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.name = "nicnatsemi",
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.type = PCI,
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.devs.dev = nics_natsemi,
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.init = nicnatsemi_init,
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};
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