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https://review.coreboot.org/flashrom.git
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Large flash chips usually support special instructions to work with 4-bytes address directly from 3-bytes addressing mode and without do switching to 4-bytes mode. There are 13h (4BA Read), 12h (4BA Program) and 21h,5Ch,DCh (4BA Erase), correspondingly. However not all these instructions are supported by all large flash chips. Some chips support 13h only, some 13h,12h,21h and DCh, but not 5Ch. This depends on the manufacturer of the chip. This patch provides code to use direct 4-bytes addressing instructions. This code should work but it tested partially only. My W25Q256FV has support for 4BA_Read (13h), but doesn't have support 4BA_Program (12h) and 4BA_Erase instructions. So, direct 4BA program and erase should be tested after. Patched files ------------- chipdrivers.h + added functions declarations for spi4ba.c flash.h + feature definitions added flashchips.c + modified definition of Winbond W25Q256BV/W25Q256FV chips flashrom.c + modified switch to 4-bytes addressing for direct-4BA instructions spi4ba.h + definitions for 4-bytes addressing JEDEC commands + functions declarations from spi4ba.c (same as in chipdrivers.h, just to see) spi4ba.c + functions for read/write/erase directly with 4-bytes address (from any mode) Change-Id: Ib51bcc5de7826b30ad697fcbb9a5152bde2c2ac9 Signed-off-by: Boris Baykov <dev@borisbaykov.com>, Russia, Jan 2014 [clg: ported from https://www.flashrom.org/pipermail/flashrom/2015-January/013198.html ] Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-on: https://review.coreboot.org/20508 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
385 lines
16 KiB
C
385 lines
16 KiB
C
/*
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* This file is part of the flashrom project.
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*
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* Copyright (C) 2000 Silicon Integrated System Corporation
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* Copyright (C) 2000 Ronald G. Minnich <rminnich@gmail.com>
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* Copyright (C) 2005-2009 coresystems GmbH
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* Copyright (C) 2006-2009 Carl-Daniel Hailfinger
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef __FLASH_H__
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#define __FLASH_H__ 1
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#include "platform.h"
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#include <inttypes.h>
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#include <stdio.h>
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#include <stdint.h>
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#include <stddef.h>
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#include <stdarg.h>
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#include <stdbool.h>
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#if IS_WINDOWS
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#include <windows.h>
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#undef min
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#undef max
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#endif
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#include "libflashrom.h"
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#include "layout.h"
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#define ERROR_PTR ((void*)-1)
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/* Error codes */
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#define ERROR_OOM -100
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#define TIMEOUT_ERROR -101
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/* TODO: check using code for correct usage of types */
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typedef uintptr_t chipaddr;
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#define PRIxPTR_WIDTH ((int)(sizeof(uintptr_t)*2))
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int register_shutdown(int (*function) (void *data), void *data);
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int shutdown_free(void *data);
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void *programmer_map_flash_region(const char *descr, uintptr_t phys_addr, size_t len);
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void programmer_unmap_flash_region(void *virt_addr, size_t len);
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void programmer_delay(unsigned int usecs);
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#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
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enum chipbustype {
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BUS_NONE = 0,
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BUS_PARALLEL = 1 << 0,
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BUS_LPC = 1 << 1,
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BUS_FWH = 1 << 2,
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BUS_SPI = 1 << 3,
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BUS_PROG = 1 << 4,
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BUS_NONSPI = BUS_PARALLEL | BUS_LPC | BUS_FWH,
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};
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/*
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* The following enum defines possible write granularities of flash chips. These tend to reflect the properties
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* of the actual hardware not necesserily the write function(s) defined by the respective struct flashchip.
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* The latter might (and should) be more precisely specified, e.g. they might bail out early if their execution
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* would result in undefined chip contents.
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*/
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enum write_granularity {
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/* We assume 256 byte granularity by default. */
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write_gran_256bytes = 0,/* If less than 256 bytes are written, the unwritten bytes are undefined. */
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write_gran_1bit, /* Each bit can be cleared individually. */
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write_gran_1byte, /* A byte can be written once. Further writes to an already written byte cause
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* its contents to be either undefined or to stay unchanged. */
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write_gran_128bytes, /* If less than 128 bytes are written, the unwritten bytes are undefined. */
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write_gran_264bytes, /* If less than 264 bytes are written, the unwritten bytes are undefined. */
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write_gran_512bytes, /* If less than 512 bytes are written, the unwritten bytes are undefined. */
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write_gran_528bytes, /* If less than 528 bytes are written, the unwritten bytes are undefined. */
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write_gran_1024bytes, /* If less than 1024 bytes are written, the unwritten bytes are undefined. */
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write_gran_1056bytes, /* If less than 1056 bytes are written, the unwritten bytes are undefined. */
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write_gran_1byte_implicit_erase, /* EEPROMs and other chips with implicit erase and 1-byte writes. */
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};
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/*
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* How many different contiguous runs of erase blocks with one size each do
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* we have for a given erase function?
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*/
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#define NUM_ERASEREGIONS 5
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/*
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* How many different erase functions do we have per chip?
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* Atmel AT25FS010 has 6 different functions.
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*/
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#define NUM_ERASEFUNCTIONS 6
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/* Feature bits used for non-SPI only */
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#define FEATURE_REGISTERMAP (1 << 0)
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#define FEATURE_LONG_RESET (0 << 4)
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#define FEATURE_SHORT_RESET (1 << 4)
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#define FEATURE_EITHER_RESET FEATURE_LONG_RESET
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#define FEATURE_RESET_MASK (FEATURE_LONG_RESET | FEATURE_SHORT_RESET)
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#define FEATURE_ADDR_FULL (0 << 2)
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#define FEATURE_ADDR_MASK (3 << 2)
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#define FEATURE_ADDR_2AA (1 << 2)
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#define FEATURE_ADDR_AAA (2 << 2)
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#define FEATURE_ADDR_SHIFTED (1 << 5)
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/* Feature bits used for SPI only */
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#define FEATURE_WRSR_EWSR (1 << 6)
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#define FEATURE_WRSR_WREN (1 << 7)
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#define FEATURE_WRSR_EITHER (FEATURE_WRSR_EWSR | FEATURE_WRSR_WREN)
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#define FEATURE_OTP (1 << 8)
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#define FEATURE_QPI (1 << 9)
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/* Feature bits used for 4-bytes addressing mode */
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#define FEATURE_4BA_SUPPORT (1 << 10)
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#define FEATURE_4BA_ONLY (1 << 11)
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#define FEATURE_4BA_EXTENDED_ADDR_REG (1 << 12)
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#define FEATURE_4BA_DIRECT_READ (1 << 13)
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#define FEATURE_4BA_DIRECT_WRITE (1 << 14)
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#define FEATURE_4BA_ALL_ERASERS_DIRECT (1 << 15)
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#define FEATURE_4BA_ALL_DIRECT (FEATURE_4BA_DIRECT_READ | FEATURE_4BA_DIRECT_WRITE | FEATURE_4BA_ALL_ERASERS_DIRECT)
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enum test_state {
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OK = 0,
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NT = 1, /* Not tested */
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BAD, /* Known to not work */
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DEP, /* Support depends on configuration (e.g. Intel flash descriptor) */
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NA, /* Not applicable (e.g. write support on ROM chips) */
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};
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#define TEST_UNTESTED (struct tested){ .probe = NT, .read = NT, .erase = NT, .write = NT }
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#define TEST_OK_PROBE (struct tested){ .probe = OK, .read = NT, .erase = NT, .write = NT }
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#define TEST_OK_PR (struct tested){ .probe = OK, .read = OK, .erase = NT, .write = NT }
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#define TEST_OK_PRE (struct tested){ .probe = OK, .read = OK, .erase = OK, .write = NT }
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#define TEST_OK_PREW (struct tested){ .probe = OK, .read = OK, .erase = OK, .write = OK }
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#define TEST_BAD_PROBE (struct tested){ .probe = BAD, .read = NT, .erase = NT, .write = NT }
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#define TEST_BAD_PR (struct tested){ .probe = BAD, .read = BAD, .erase = NT, .write = NT }
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#define TEST_BAD_PRE (struct tested){ .probe = BAD, .read = BAD, .erase = BAD, .write = NT }
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#define TEST_BAD_PREW (struct tested){ .probe = BAD, .read = BAD, .erase = BAD, .write = BAD }
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struct flashrom_flashctx;
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#define flashctx flashrom_flashctx /* TODO: Agree on a name and convert all occurences. */
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typedef int (erasefunc_t)(struct flashctx *flash, unsigned int addr, unsigned int blocklen);
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struct flashchip {
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const char *vendor;
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const char *name;
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enum chipbustype bustype;
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/*
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* With 32bit manufacture_id and model_id we can cover IDs up to
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* (including) the 4th bank of JEDEC JEP106W Standard Manufacturer's
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* Identification code.
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*/
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uint32_t manufacture_id;
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uint32_t model_id;
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/* Total chip size in kilobytes */
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unsigned int total_size;
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/* Chip page size in bytes */
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unsigned int page_size;
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int feature_bits;
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/* set of function pointers to use in 4-bytes addressing mode */
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struct four_bytes_addr_funcs_set {
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int (*enter_4ba) (struct flashctx *flash);
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int (*read_nbyte) (struct flashctx *flash, unsigned int addr, uint8_t *bytes, unsigned int len);
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int (*program_byte) (struct flashctx *flash, unsigned int addr, const uint8_t databyte);
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int (*program_nbyte) (struct flashctx *flash, unsigned int addr, const uint8_t *bytes, unsigned int len);
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} four_bytes_addr_funcs;
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/* Indicate how well flashrom supports different operations of this flash chip. */
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struct tested {
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enum test_state probe;
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enum test_state read;
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enum test_state erase;
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enum test_state write;
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} tested;
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int (*probe) (struct flashctx *flash);
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/* Delay after "enter/exit ID mode" commands in microseconds.
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* NB: negative values have special meanings, see TIMING_* below.
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*/
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signed int probe_timing;
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/*
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* Erase blocks and associated erase function. Any chip erase function
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* is stored as chip-sized virtual block together with said function.
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* The first one that fits will be chosen. There is currently no way to
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* influence that behaviour. For testing just comment out the other
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* elements or set the function pointer to NULL.
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*/
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struct block_eraser {
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struct eraseblock {
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unsigned int size; /* Eraseblock size in bytes */
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unsigned int count; /* Number of contiguous blocks with that size */
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} eraseblocks[NUM_ERASEREGIONS];
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/* a block_erase function should try to erase one block of size
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* 'blocklen' at address 'blockaddr' and return 0 on success. */
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int (*block_erase) (struct flashctx *flash, unsigned int blockaddr, unsigned int blocklen);
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} block_erasers[NUM_ERASEFUNCTIONS];
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int (*printlock) (struct flashctx *flash);
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int (*unlock) (struct flashctx *flash);
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int (*write) (struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len);
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int (*read) (struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len);
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struct voltage {
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uint16_t min;
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uint16_t max;
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} voltage;
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enum write_granularity gran;
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};
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struct flashrom_flashctx {
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struct flashchip *chip;
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/* FIXME: The memory mappings should be saved in a more structured way. */
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/* The physical_* fields store the respective addresses in the physical address space of the CPU. */
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uintptr_t physical_memory;
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/* The virtual_* fields store where the respective physical address is mapped into flashrom's address
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* space. A value equivalent to (chipaddr)ERROR_PTR indicates an invalid mapping (or none at all). */
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chipaddr virtual_memory;
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/* Some flash devices have an additional register space; semantics are like above. */
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uintptr_t physical_registers;
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chipaddr virtual_registers;
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struct registered_master *mst;
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const struct flashrom_layout *layout;
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struct single_layout fallback_layout;
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struct {
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bool force;
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bool force_boardmismatch;
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bool verify_after_write;
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bool verify_whole_chip;
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} flags;
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};
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/* Timing used in probe routines. ZERO is -2 to differentiate between an unset
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* field and zero delay.
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*
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* SPI devices will always have zero delay and ignore this field.
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*/
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#define TIMING_FIXME -1
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/* this is intentionally same value as fixme */
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#define TIMING_IGNORED -1
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#define TIMING_ZERO -2
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extern const struct flashchip flashchips[];
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extern const unsigned int flashchips_size;
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void chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr);
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void chip_writew(const struct flashctx *flash, uint16_t val, chipaddr addr);
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void chip_writel(const struct flashctx *flash, uint32_t val, chipaddr addr);
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void chip_writen(const struct flashctx *flash, const uint8_t *buf, chipaddr addr, size_t len);
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uint8_t chip_readb(const struct flashctx *flash, const chipaddr addr);
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uint16_t chip_readw(const struct flashctx *flash, const chipaddr addr);
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uint32_t chip_readl(const struct flashctx *flash, const chipaddr addr);
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void chip_readn(const struct flashctx *flash, uint8_t *buf, const chipaddr addr, size_t len);
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/* print.c */
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int print_supported(void);
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void print_supported_wiki(void);
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/* helpers.c */
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uint32_t address_to_bits(uint32_t addr);
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int bitcount(unsigned long a);
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int max(int a, int b);
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int min(int a, int b);
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char *strcat_realloc(char *dest, const char *src);
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void tolower_string(char *str);
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#ifdef __MINGW32__
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char* strtok_r(char *str, const char *delim, char **nextp);
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#endif
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#if defined(__DJGPP__) || (!defined(__LIBPAYLOAD__) && !defined(HAVE_STRNLEN))
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size_t strnlen(const char *str, size_t n);
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#endif
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/* flashrom.c */
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extern const char flashrom_version[];
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extern const char *chip_to_probe;
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char *flashbuses_to_text(enum chipbustype bustype);
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int map_flash(struct flashctx *flash);
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void unmap_flash(struct flashctx *flash);
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int read_memmapped(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len);
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int erase_flash(struct flashctx *flash);
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int probe_flash(struct registered_master *mst, int startchip, struct flashctx *fill_flash, int force);
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int read_flash_to_file(struct flashctx *flash, const char *filename);
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char *extract_param(const char *const *haystack, const char *needle, const char *delim);
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int verify_range(struct flashctx *flash, const uint8_t *cmpbuf, unsigned int start, unsigned int len);
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int need_erase(const uint8_t *have, const uint8_t *want, unsigned int len, enum write_granularity gran);
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void print_version(void);
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void print_buildinfo(void);
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void print_banner(void);
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void list_programmers_linebreak(int startcol, int cols, int paren);
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int selfcheck(void);
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int read_buf_from_file(unsigned char *buf, unsigned long size, const char *filename);
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int write_buf_to_file(const unsigned char *buf, unsigned long size, const char *filename);
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int prepare_flash_access(struct flashctx *, bool read_it, bool write_it, bool erase_it, bool verify_it);
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void finalize_flash_access(struct flashctx *);
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int do_read(struct flashctx *, const char *filename);
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int do_erase(struct flashctx *);
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int do_write(struct flashctx *, const char *const filename);
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int do_verify(struct flashctx *, const char *const filename);
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/* Something happened that shouldn't happen, but we can go on. */
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#define ERROR_NONFATAL 0x100
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/* Something happened that shouldn't happen, we'll abort. */
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#define ERROR_FATAL -0xee
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#define ERROR_FLASHROM_BUG -200
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/* We reached one of the hardcoded limits of flashrom. This can be fixed by
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* increasing the limit of a compile-time allocation or by switching to dynamic
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* allocation.
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* Note: If this warning is triggered, check first for runaway registrations.
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*/
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#define ERROR_FLASHROM_LIMIT -201
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/* cli_common.c */
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void print_chip_support_status(const struct flashchip *chip);
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/* cli_output.c */
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extern enum flashrom_log_level verbose_screen;
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extern enum flashrom_log_level verbose_logfile;
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#ifndef STANDALONE
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int open_logfile(const char * const filename);
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int close_logfile(void);
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void start_logging(void);
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#endif
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int flashrom_print_cb(enum flashrom_log_level level, const char *fmt, va_list ap);
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/* Let gcc and clang check for correct printf-style format strings. */
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int print(enum flashrom_log_level level, const char *fmt, ...)
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#ifdef __MINGW32__
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__attribute__((format(gnu_printf, 2, 3)));
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#else
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__attribute__((format(printf, 2, 3)));
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#endif
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#define msg_gerr(...) print(FLASHROM_MSG_ERROR, __VA_ARGS__) /* general errors */
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#define msg_perr(...) print(FLASHROM_MSG_ERROR, __VA_ARGS__) /* programmer errors */
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#define msg_cerr(...) print(FLASHROM_MSG_ERROR, __VA_ARGS__) /* chip errors */
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#define msg_gwarn(...) print(FLASHROM_MSG_WARN, __VA_ARGS__) /* general warnings */
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#define msg_pwarn(...) print(FLASHROM_MSG_WARN, __VA_ARGS__) /* programmer warnings */
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#define msg_cwarn(...) print(FLASHROM_MSG_WARN, __VA_ARGS__) /* chip warnings */
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#define msg_ginfo(...) print(FLASHROM_MSG_INFO, __VA_ARGS__) /* general info */
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#define msg_pinfo(...) print(FLASHROM_MSG_INFO, __VA_ARGS__) /* programmer info */
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#define msg_cinfo(...) print(FLASHROM_MSG_INFO, __VA_ARGS__) /* chip info */
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#define msg_gdbg(...) print(FLASHROM_MSG_DEBUG, __VA_ARGS__) /* general debug */
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#define msg_pdbg(...) print(FLASHROM_MSG_DEBUG, __VA_ARGS__) /* programmer debug */
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#define msg_cdbg(...) print(FLASHROM_MSG_DEBUG, __VA_ARGS__) /* chip debug */
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#define msg_gdbg2(...) print(FLASHROM_MSG_DEBUG2, __VA_ARGS__) /* general debug2 */
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#define msg_pdbg2(...) print(FLASHROM_MSG_DEBUG2, __VA_ARGS__) /* programmer debug2 */
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#define msg_cdbg2(...) print(FLASHROM_MSG_DEBUG2, __VA_ARGS__) /* chip debug2 */
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#define msg_gspew(...) print(FLASHROM_MSG_SPEW, __VA_ARGS__) /* general debug spew */
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#define msg_pspew(...) print(FLASHROM_MSG_SPEW, __VA_ARGS__) /* programmer debug spew */
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#define msg_cspew(...) print(FLASHROM_MSG_SPEW, __VA_ARGS__) /* chip debug spew */
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/* layout.c */
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int register_include_arg(char *name);
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int read_romlayout(const char *name);
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int normalize_romentries(const struct flashctx *flash);
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void layout_cleanup(void);
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/* spi.c */
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struct spi_command {
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unsigned int writecnt;
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unsigned int readcnt;
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const unsigned char *writearr;
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unsigned char *readarr;
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};
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int spi_send_command(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr);
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int spi_send_multicommand(struct flashctx *flash, struct spi_command *cmds);
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uint32_t spi_get_valid_read_addr(struct flashctx *flash);
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enum chipbustype get_buses_supported(void);
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#endif /* !__FLASH_H__ */
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