mirror of
https://review.coreboot.org/flashrom.git
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a2faddf7d3
Pcidev_init() now returns struct pci_device * instead of a BAR stored in PCI config space. This allows for real error checking instead of having exit(1) everywhere in pcidev.c. Thanks to Niklas Söderlund for coming up with the original error handling patch which was slightly modified and folded into this patch. Move the declaration of struct pci_device in programmer.h before the first user. Corresponding to flashrom svn r1644. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
133 lines
4.3 KiB
C
133 lines
4.3 KiB
C
/*
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* This file is part of the flashrom project.
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*
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* Copyright (C) 2011 Carl-Daniel Hailfinger
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/* Datasheet: http://download.intel.com/design/network/datashts/82559_Fast_Ethernet_Multifunction_PCI_Cardbus_Controller_Datasheet.pdf */
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#include <stdlib.h>
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#include "flash.h"
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#include "programmer.h"
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#include "hwaccess.h"
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uint8_t *nicintel_bar;
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uint8_t *nicintel_control_bar;
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const struct dev_entry nics_intel[] = {
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{PCI_VENDOR_ID_INTEL, 0x1209, NT, "Intel", "8255xER/82551IT Fast Ethernet Controller"},
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{PCI_VENDOR_ID_INTEL, 0x1229, OK, "Intel", "82557/8/9/0/1 Ethernet Pro 100"},
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{0},
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};
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/* Arbitrary limit, taken from the datasheet I just had lying around.
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* 128 kByte on the 82559 device. Or not. Depends on whom you ask.
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*/
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#define NICINTEL_MEMMAP_SIZE (128 * 1024)
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#define NICINTEL_MEMMAP_MASK (NICINTEL_MEMMAP_SIZE - 1)
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#define NICINTEL_CONTROL_MEMMAP_SIZE 0x10
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#define CSR_FCR 0x0c
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static void nicintel_chip_writeb(const struct flashctx *flash, uint8_t val,
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chipaddr addr);
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static uint8_t nicintel_chip_readb(const struct flashctx *flash,
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const chipaddr addr);
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static const struct par_programmer par_programmer_nicintel = {
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.chip_readb = nicintel_chip_readb,
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.chip_readw = fallback_chip_readw,
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.chip_readl = fallback_chip_readl,
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.chip_readn = fallback_chip_readn,
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.chip_writeb = nicintel_chip_writeb,
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.chip_writew = fallback_chip_writew,
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.chip_writel = fallback_chip_writel,
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.chip_writen = fallback_chip_writen,
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};
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static int nicintel_shutdown(void *data)
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{
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physunmap(nicintel_control_bar, NICINTEL_CONTROL_MEMMAP_SIZE);
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physunmap(nicintel_bar, NICINTEL_MEMMAP_SIZE);
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return 0;
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}
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int nicintel_init(void)
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{
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struct pci_dev *dev = NULL;
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uintptr_t addr;
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/* Needed only for PCI accesses on some platforms.
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* FIXME: Refactor that into get_mem_perms/rget_io_perms/get_pci_perms?
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*/
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if (rget_io_perms())
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return 1;
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/* FIXME: BAR2 is not available if the device uses the CardBus function. */
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dev = pcidev_init(nics_intel, PCI_BASE_ADDRESS_2);
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if (!dev)
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return 1;
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addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_2);
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nicintel_bar = physmap("Intel NIC flash", addr, NICINTEL_MEMMAP_SIZE);
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if (nicintel_bar == ERROR_PTR)
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goto error_out_unmap;
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addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0);
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/* FIXME: This is not an aligned mapping. Use 4k? */
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nicintel_control_bar = physmap("Intel NIC control/status reg",
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addr, NICINTEL_CONTROL_MEMMAP_SIZE);
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if (nicintel_control_bar == ERROR_PTR)
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goto error_out;
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if (register_shutdown(nicintel_shutdown, NULL))
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return 1;
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/* FIXME: This register is pretty undocumented in all publicly available
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* documentation from Intel. Let me quote the complete info we have:
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* "Flash Control Register: The Flash Control register allows the CPU to
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* enable writes to an external Flash. The Flash Control Register is a
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* 32-bit field that allows access to an external Flash device."
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* Ah yes, we also know where it is, but we have absolutely _no_ idea
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* what we should do with it. Write 0x0001 because we have nothing
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* better to do with our time.
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*/
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pci_rmmio_writew(0x0001, nicintel_control_bar + CSR_FCR);
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max_rom_decode.parallel = NICINTEL_MEMMAP_SIZE;
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register_par_programmer(&par_programmer_nicintel, BUS_PARALLEL);
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return 0;
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error_out_unmap:
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physunmap(nicintel_bar, NICINTEL_MEMMAP_SIZE);
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error_out:
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return 1;
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}
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static void nicintel_chip_writeb(const struct flashctx *flash, uint8_t val,
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chipaddr addr)
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{
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pci_mmio_writeb(val, nicintel_bar + (addr & NICINTEL_MEMMAP_MASK));
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}
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static uint8_t nicintel_chip_readb(const struct flashctx *flash,
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const chipaddr addr)
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{
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return pci_mmio_readb(nicintel_bar + (addr & NICINTEL_MEMMAP_MASK));
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}
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