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https://review.coreboot.org/flashrom.git
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ec489e4ec6
ICH SPI has the ability to restrict SPI read/write accesses to a given address range. The low end of the range is configurable by the BIOS (and by flashrom if the BIOS didn't lock down the flash interface), the high end of the range is 0xffffff (2^24-1). This patch checks for an address range restriction and uses the low end of the allowed range as base for SPI reads. A similar workaround for REMS/RES opcodes has been committed in r500. This fixes read on the Intel D945GCLF mainboard where the stock BIOS enforces a restricted address range. Please note that writes need the same fix, but for architectural reasons that fix will be merged once partial write is available. Corresponding to flashrom svn r1170. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Tested by David Hendricks on the Intel D945GCLF mainboard, results at http://paste.flashrom.org/view.php?id=79 Acked-by: David Hendricks <dhendrix@google.com>
299 lines
8.1 KiB
C
299 lines
8.1 KiB
C
/*
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* This file is part of the flashrom project.
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*
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* Copyright (C) 2007, 2008, 2009 Carl-Daniel Hailfinger
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* Copyright (C) 2008 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/*
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* Contains the generic SPI framework
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*/
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#include <string.h>
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#include "flash.h"
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#include "flashchips.h"
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#include "chipdrivers.h"
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#include "programmer.h"
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#include "spi.h"
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enum spi_controller spi_controller = SPI_CONTROLLER_NONE;
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const struct spi_programmer spi_programmer[] = {
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{ /* SPI_CONTROLLER_NONE */
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.command = NULL,
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.multicommand = NULL,
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.read = NULL,
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.write_256 = NULL,
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},
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#if CONFIG_INTERNAL == 1
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#if defined(__i386__) || defined(__x86_64__)
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{ /* SPI_CONTROLLER_ICH7 */
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.command = ich_spi_send_command,
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.multicommand = ich_spi_send_multicommand,
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.read = ich_spi_read,
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.write_256 = ich_spi_write_256,
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},
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{ /* SPI_CONTROLLER_ICH9 */
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.command = ich_spi_send_command,
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.multicommand = ich_spi_send_multicommand,
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.read = ich_spi_read,
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.write_256 = ich_spi_write_256,
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},
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{ /* SPI_CONTROLLER_IT87XX */
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.command = it8716f_spi_send_command,
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.multicommand = default_spi_send_multicommand,
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.read = it8716f_spi_chip_read,
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.write_256 = it8716f_spi_chip_write_256,
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},
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{ /* SPI_CONTROLLER_SB600 */
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.command = sb600_spi_send_command,
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.multicommand = default_spi_send_multicommand,
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.read = sb600_spi_read,
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.write_256 = sb600_spi_write_256,
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},
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{ /* SPI_CONTROLLER_VIA */
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.command = ich_spi_send_command,
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.multicommand = ich_spi_send_multicommand,
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.read = ich_spi_read,
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.write_256 = ich_spi_write_256,
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},
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{ /* SPI_CONTROLLER_WBSIO */
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.command = wbsio_spi_send_command,
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.multicommand = default_spi_send_multicommand,
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.read = wbsio_spi_read,
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.write_256 = spi_chip_write_1_new,
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},
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{ /* SPI_CONTROLLER_MCP6X_BITBANG */
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.command = bitbang_spi_send_command,
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.multicommand = default_spi_send_multicommand,
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.read = bitbang_spi_read,
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.write_256 = bitbang_spi_write_256,
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},
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#endif
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#endif
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#if CONFIG_FT2232_SPI == 1
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{ /* SPI_CONTROLLER_FT2232 */
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.command = ft2232_spi_send_command,
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.multicommand = default_spi_send_multicommand,
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.read = ft2232_spi_read,
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.write_256 = ft2232_spi_write_256,
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},
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#endif
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#if CONFIG_DUMMY == 1
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{ /* SPI_CONTROLLER_DUMMY */
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.command = dummy_spi_send_command,
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.multicommand = default_spi_send_multicommand,
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.read = dummy_spi_read,
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.write_256 = dummy_spi_write_256,
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},
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#endif
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#if CONFIG_BUSPIRATE_SPI == 1
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{ /* SPI_CONTROLLER_BUSPIRATE */
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.command = buspirate_spi_send_command,
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.multicommand = default_spi_send_multicommand,
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.read = buspirate_spi_read,
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.write_256 = buspirate_spi_write_256,
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},
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#endif
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#if CONFIG_DEDIPROG == 1
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{ /* SPI_CONTROLLER_DEDIPROG */
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.command = dediprog_spi_send_command,
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.multicommand = default_spi_send_multicommand,
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.read = dediprog_spi_read,
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.write_256 = spi_chip_write_1_new,
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},
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#endif
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#if CONFIG_RAYER_SPI == 1
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{ /* SPI_CONTROLLER_RAYER */
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.command = bitbang_spi_send_command,
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.multicommand = default_spi_send_multicommand,
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.read = bitbang_spi_read,
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.write_256 = bitbang_spi_write_256,
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},
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#endif
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#if CONFIG_NICINTEL_SPI == 1
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{ /* SPI_CONTROLLER_NICINTEL */
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.command = bitbang_spi_send_command,
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.multicommand = default_spi_send_multicommand,
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.read = bitbang_spi_read,
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.write_256 = bitbang_spi_write_256,
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},
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#endif
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{}, /* This entry corresponds to SPI_CONTROLLER_INVALID. */
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};
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const int spi_programmer_count = ARRAY_SIZE(spi_programmer);
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int spi_send_command(unsigned int writecnt, unsigned int readcnt,
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const unsigned char *writearr, unsigned char *readarr)
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{
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if (!spi_programmer[spi_controller].command) {
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msg_perr("%s called, but SPI is unsupported on this "
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"hardware. Please report a bug at "
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"flashrom@flashrom.org\n", __func__);
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return 1;
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}
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return spi_programmer[spi_controller].command(writecnt, readcnt,
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writearr, readarr);
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}
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int spi_send_multicommand(struct spi_command *cmds)
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{
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if (!spi_programmer[spi_controller].multicommand) {
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msg_perr("%s called, but SPI is unsupported on this "
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"hardware. Please report a bug at "
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"flashrom@flashrom.org\n", __func__);
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return 1;
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}
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return spi_programmer[spi_controller].multicommand(cmds);
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}
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int default_spi_send_command(unsigned int writecnt, unsigned int readcnt,
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const unsigned char *writearr, unsigned char *readarr)
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{
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struct spi_command cmd[] = {
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{
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.writecnt = writecnt,
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.readcnt = readcnt,
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.writearr = writearr,
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.readarr = readarr,
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}, {
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.writecnt = 0,
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.writearr = NULL,
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.readcnt = 0,
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.readarr = NULL,
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}};
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return spi_send_multicommand(cmd);
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}
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int default_spi_send_multicommand(struct spi_command *cmds)
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{
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int result = 0;
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for (; (cmds->writecnt || cmds->readcnt) && !result; cmds++) {
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result = spi_send_command(cmds->writecnt, cmds->readcnt,
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cmds->writearr, cmds->readarr);
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}
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return result;
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}
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int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len)
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{
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int addrbase = 0;
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if (!spi_programmer[spi_controller].read) {
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msg_perr("%s called, but SPI read is unsupported on this "
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"hardware. Please report a bug at "
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"flashrom@flashrom.org\n", __func__);
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return 1;
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}
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/* Check if the chip fits between lowest valid and highest possible
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* address. Highest possible address with the current SPI implementation
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* means 0xffffff, the highest unsigned 24bit number.
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*/
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addrbase = spi_get_valid_read_addr();
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if (addrbase + flash->total_size * 1024 > (1 << 24)) {
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msg_perr("Flash chip size exceeds the allowed access window. ");
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msg_perr("Read will probably fail.\n");
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/* Try to get the best alignment subject to constraints. */
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addrbase = (1 << 24) - flash->total_size * 1024;
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}
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/* Check if alignment is native (at least the largest power of two which
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* is a factor of the mapped size of the chip).
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*/
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if (ffs(flash->total_size * 1024) > (ffs(addrbase) ? : 33)) {
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msg_perr("Flash chip is not aligned natively in the allowed "
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"access window.\n");
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msg_perr("Read will probably return garbage.\n");
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}
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return spi_programmer[spi_controller].read(flash, buf, addrbase + start, len);
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}
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/*
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* Program chip using page (256 bytes) programming.
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* Some SPI masters can't do this, they use single byte programming instead.
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* The redirect to single byte programming is achieved by setting
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* .write_256 = spi_chip_write_1
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*/
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/* real chunksize is up to 256, logical chunksize is 256 */
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int spi_chip_write_256_new(struct flashchip *flash, uint8_t *buf, int start, int len)
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{
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if (!spi_programmer[spi_controller].write_256) {
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msg_perr("%s called, but SPI page write is unsupported on this "
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"hardware. Please report a bug at "
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"flashrom@flashrom.org\n", __func__);
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return 1;
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}
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return spi_programmer[spi_controller].write_256(flash, buf, start, len);
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}
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/* Wrapper function until the generic code is converted to partial writes. */
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int spi_chip_write_256(struct flashchip *flash, uint8_t *buf)
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{
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int ret;
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msg_pinfo("Erasing flash before programming... ");
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if (erase_flash(flash)) {
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msg_perr("ERASE FAILED!\n");
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return -1;
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}
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msg_pinfo("done.\n");
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msg_pinfo("Programming flash... ");
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ret = spi_chip_write_256_new(flash, buf, 0, flash->total_size * 1024);
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if (!ret)
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msg_pinfo("done.\n");
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else
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msg_pinfo("\n");
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return ret;
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}
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/*
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* Get the lowest allowed address for read accesses. This often happens to
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* be the lowest allowed address for all commands which take an address.
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* This is a programmer limitation.
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*/
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uint32_t spi_get_valid_read_addr(void)
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{
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switch (spi_controller) {
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#if CONFIG_INTERNAL == 1
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#if defined(__i386__) || defined(__x86_64__)
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case SPI_CONTROLLER_ICH7:
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/* Return BBAR for ICH chipsets. */
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return ichspi_bbar;
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#endif
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#endif
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default:
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return 0;
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}
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}
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