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37c4252ef7
Allow specification of an alternate base address with flashrom -p rayer_spi:iobase=0x278 Any base address is allowed as long as it is nonzero, below 65536 and a multiple of four. Read speed is now on par with original spipgm.exe. Corresponding to flashrom svn r1188. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Tested-by: Martin Rehak <rayer@seznam.cz> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
146 lines
4.1 KiB
C
146 lines
4.1 KiB
C
/*
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* This file is part of the flashrom project.
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*
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* Copyright (C) 2009,2010 Carl-Daniel Hailfinger
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/* Driver for the SPIPGM hardware by "RayeR" Martin Rehak.
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* See http://rayer.ic.cz/elektro/spipgm.htm for schematics and instructions.
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*/
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/* This driver uses non-portable direct I/O port accesses which won't work on
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* any non-x86 platform, and even on x86 there is a high chance there will be
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* collisions with any loaded parallel port drivers.
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* The big advantage of direct port I/O is OS independence and speed because
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* most OS parport drivers will perform many unnecessary accesses although
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* this driver just treats the parallel port as a GPIO set.
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*/
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#if defined(__i386__) || defined(__x86_64__)
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#include <stdlib.h>
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#include "flash.h"
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#include "programmer.h"
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/* We have two sets of pins, out and in. The numbers for both sets are
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* independent and are bitshift values, not real pin numbers.
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*/
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/* Pins for master->slave direction */
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#define SPI_CS_PIN 5
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#define SPI_SCK_PIN 6
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#define SPI_MOSI_PIN 7
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/* Pins for slave->master direction */
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#define SPI_MISO_PIN 6
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static uint16_t lpt_iobase;
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/* Cached value of last byte sent. */
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static uint8_t lpt_outbyte;
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static void rayer_bitbang_set_cs(int val)
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{
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lpt_outbyte &= ~(1 << SPI_CS_PIN);
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lpt_outbyte |= (val << SPI_CS_PIN);
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OUTB(lpt_outbyte, lpt_iobase);
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}
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static void rayer_bitbang_set_sck(int val)
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{
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lpt_outbyte &= ~(1 << SPI_SCK_PIN);
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lpt_outbyte |= (val << SPI_SCK_PIN);
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OUTB(lpt_outbyte, lpt_iobase);
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}
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static void rayer_bitbang_set_mosi(int val)
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{
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lpt_outbyte &= ~(1 << SPI_MOSI_PIN);
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lpt_outbyte |= (val << SPI_MOSI_PIN);
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OUTB(lpt_outbyte, lpt_iobase);
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}
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static int rayer_bitbang_get_miso(void)
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{
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uint8_t tmp;
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tmp = INB(lpt_iobase + 1);
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tmp = (tmp >> SPI_MISO_PIN) & 0x1;
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return tmp;
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}
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static const struct bitbang_spi_master bitbang_spi_master_rayer = {
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.type = BITBANG_SPI_MASTER_RAYER,
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.set_cs = rayer_bitbang_set_cs,
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.set_sck = rayer_bitbang_set_sck,
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.set_mosi = rayer_bitbang_set_mosi,
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.get_miso = rayer_bitbang_get_miso,
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};
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int rayer_spi_init(void)
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{
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char *portpos = NULL;
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/* Non-default port requested? */
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portpos = extract_programmer_param("iobase");
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if (portpos) {
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char *endptr = NULL;
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unsigned long tmp;
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tmp = strtoul(portpos, &endptr, 0);
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/* Port 0, port >0x10000, unaligned ports and garbage strings
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* are rejected.
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*/
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if (!tmp || (tmp >= 0x10000) || (tmp & 0x3) ||
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(*endptr != '\0')) {
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/* Using ports below 0x100 is a really bad idea, and
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* should only be done if no port between 0x100 and
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* 0xfffc works due to routing issues.
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*/
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msg_perr("Error: iobase= specified, but the I/O base "
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"given was invalid.\nIt must be a multiple of "
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"0x4 and lie between 0x100 and 0xfffc.\n");
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free(portpos);
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return 1;
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} else {
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lpt_iobase = (uint16_t)tmp;
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msg_pinfo("Non-default I/O base requested. This will "
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"not change the hardware settings.\n");
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}
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} else {
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/* Pick a default value for the I/O base. */
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lpt_iobase = 0x378;
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}
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free(portpos);
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msg_pdbg("Using address 0x%x as I/O base for parallel port access.\n",
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lpt_iobase);
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get_io_perms();
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/* Get the initial value before writing to any line. */
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lpt_outbyte = INB(lpt_iobase);
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/* Zero halfperiod delay. */
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if (bitbang_spi_init(&bitbang_spi_master_rayer, 0))
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return 1;
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buses_supported = CHIP_BUSTYPE_SPI;
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spi_controller = SPI_CONTROLLER_RAYER;
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return 0;
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}
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#else
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#error PCI port I/O access is not supported on this architecture yet.
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#endif
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