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a3519561bd
This may seem too big just to support yet another flash chip, but in
reality it brings support for whole new family of S25FS
Spansion/Cypress flash chips. These chips require handling of some
special status registers for erasing or writing, with very specific
timing checks in place.
For example, WIP status bit will remain being set to 1 if erase or
programming errors occur, and in that case chip 'software reset' has
to be performed otherwise the chip will remain unresponsive to all
further commands. Also, special CR3NV register (Configuration Register
3 Nonvolatile) status bits needs to be read and set by using RDAR
(ReaD Any Register) and WRAR (WRite Any Register) OP commands, and
these states are needed to determine which type of reset feature is
enabled at the time (legacy or S25FS type) in the first place,
determine whether Uniform or Hybrid sector architecture is used
at the time, or set programming buffer address wrap point (256 or 512
bytes). Furthermore, S25FS chip status register has to be restored to
its original state (hence that ugly CHIP_RESTORE_CALLBACK) following
erasing or writing, failing to do so may result in host being unable
to access data on the chip at all.
Finally, although this brings support for the whole family of chips,
I only have one such chip to do the actual testing, S25FS128S (Small
Sectors), which I had fully tested on ch341a and FT4232H programmers,
with confirmed working probe, read, erase and write.
Full summary of changes are here:
flashchips:
add new flashchip sctructure property:
.reset
add chip definitions:
S25FS128S Large Sectors
S25FS128S Small Sectors
flash:
add macro (chip_restore_func_data call-back):
CHIP_RESTORE_CALLBACK
flashrom:
add struct:
chip_restore_func_data
add call-back function:
register_chip_restore
spi:
add OP codes:
CMD_RDAR, CMD_WRAR, CMD_WRAR_LEN, CMD_RSTEN, CMD_RST
add register bit function definitions:
CR3NV_ADDR, CR3NV_20H_NV
add timers:
T_W, T_RPH, T_SE
spi25:
refactor (based on chromiumos implementation) function:
spi_poll_wip
port these functions from chromiumos:
probe_spi_big_spansion
s25fs_software_reset
s25f_legacy_software_reset
s25fs_block_erase_d8
spi25_statusreg:
port these functions from chromiumos:
spi_restore_status
s25fs_read_cr
s25fs_write_cr
s25fs_restore_cr3nv
Most of the ported functions are originally from s25f.c found at
https://chromium.googlesource.com/chromiumos/third_party/flashrom
with exception of spi_restore_status which is defined in
spi25_statusreg.c. The rest of macros and OP codes are defined in
same files as in this commit.
Change-Id: If659290874a4b9db6e71256bdef382d31b288e72
Signed-off-by: Samir Ibradzic <sibradzic@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/39822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
209 lines
5.9 KiB
C
209 lines
5.9 KiB
C
/*
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* This file is part of the flashrom project.
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*
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* Copyright (C) 2007, 2008 Carl-Daniel Hailfinger
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __SPI_H__
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#define __SPI_H__ 1
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/*
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* Contains the generic SPI headers
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*/
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#define JEDEC_MAX_ADDR_LEN 0x04
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/* Read Electronic ID */
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#define JEDEC_RDID 0x9f
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#define JEDEC_RDID_OUTSIZE 0x01
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/* INSIZE may be 0x04 for some chips*/
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#define JEDEC_RDID_INSIZE 0x03
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/* Some ST M95X model */
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#define ST_M95_RDID 0x83
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#define ST_M95_RDID_3BA_OUTSIZE 0x04 /* 8b op, 24bit addr where size >64KiB */
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#define ST_M95_RDID_2BA_OUTSIZE 0x03 /* 8b op, 16bit addr where size <=64KiB */
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#define ST_M95_RDID_OUTSIZE_MAX 0x04 /* ST_M95_RDID_3BA_OUTSIZE */
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#define ST_M95_RDID_INSIZE 0x03
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/* Some Atmel AT25F* models have bit 3 as don't care bit in commands */
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#define AT25F_RDID 0x15 /* 0x15 or 0x1d */
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#define AT25F_RDID_OUTSIZE 0x01
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#define AT25F_RDID_INSIZE 0x02
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/* Read Electronic Manufacturer Signature */
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#define JEDEC_REMS 0x90
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#define JEDEC_REMS_OUTSIZE 0x04
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#define JEDEC_REMS_INSIZE 0x02
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/* Read Serial Flash Discoverable Parameters (SFDP) */
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#define JEDEC_SFDP 0x5a
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#define JEDEC_SFDP_OUTSIZE 0x05 /* 8b op, 24b addr, 8b dummy */
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/* JEDEC_SFDP_INSIZE : any length */
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/* Read Electronic Signature */
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#define JEDEC_RES 0xab
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#define JEDEC_RES_OUTSIZE 0x04
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/* INSIZE may be 0x02 for some chips*/
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#define JEDEC_RES_INSIZE 0x01
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/* Write Enable */
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#define JEDEC_WREN 0x06
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#define JEDEC_WREN_OUTSIZE 0x01
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#define JEDEC_WREN_INSIZE 0x00
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/* Write Disable */
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#define JEDEC_WRDI 0x04
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#define JEDEC_WRDI_OUTSIZE 0x01
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#define JEDEC_WRDI_INSIZE 0x00
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/* Chip Erase 0x60 is supported by Macronix/SST chips. */
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#define JEDEC_CE_60 0x60
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#define JEDEC_CE_60_OUTSIZE 0x01
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#define JEDEC_CE_60_INSIZE 0x00
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/* Chip Erase 0x62 is supported by Atmel AT25F chips. */
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#define JEDEC_CE_62 0x62
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#define JEDEC_CE_62_OUTSIZE 0x01
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#define JEDEC_CE_62_INSIZE 0x00
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/* Chip Erase 0xc7 is supported by SST/ST/EON/Macronix chips. */
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#define JEDEC_CE_C7 0xc7
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#define JEDEC_CE_C7_OUTSIZE 0x01
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#define JEDEC_CE_C7_INSIZE 0x00
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/* Block Erase 0x50 is supported by Atmel AT26DF chips. */
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#define JEDEC_BE_50 0x50
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#define JEDEC_BE_50_OUTSIZE 0x04
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#define JEDEC_BE_50_INSIZE 0x00
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/* Block Erase 0x52 is supported by SST and old Atmel chips. */
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#define JEDEC_BE_52 0x52
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#define JEDEC_BE_52_OUTSIZE 0x04
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#define JEDEC_BE_52_INSIZE 0x00
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/* Block Erase 0x81 is supported by Atmel AT26DF chips. */
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#define JEDEC_BE_81 0x81
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#define JEDEC_BE_81_OUTSIZE 0x04
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#define JEDEC_BE_81_INSIZE 0x00
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/* Block Erase 0xc4 is supported by Micron chips. */
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#define JEDEC_BE_C4 0xc4
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#define JEDEC_BE_C4_OUTSIZE 0x04
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#define JEDEC_BE_C4_INSIZE 0x00
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/* Block Erase 0xd8 is supported by EON/Macronix/Spansion chips. */
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#define JEDEC_BE_D8 0xd8
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#define JEDEC_BE_D8_OUTSIZE 0x04
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#define JEDEC_BE_D8_INSIZE 0x00
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/* Block Erase 0xd7 is supported by PMC chips. */
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#define JEDEC_BE_D7 0xd7
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#define JEDEC_BE_D7_OUTSIZE 0x04
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#define JEDEC_BE_D7_INSIZE 0x00
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/* Sector Erase 0x20 is supported by Macronix/SST chips. */
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#define JEDEC_SE 0x20
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#define JEDEC_SE_OUTSIZE 0x04
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#define JEDEC_SE_INSIZE 0x00
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/* RADR, WRAR, RSTEN, RST & CR3NV OPs and timers on Spansion S25FS chips */
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#define CMD_RDAR 0x65
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#define CMD_WRAR 0x71
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#define CMD_WRAR_LEN 5
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#define CMD_RSTEN 0x66
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#define CMD_RST 0x99
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#define CR3NV_ADDR 0x000004
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#define CR3NV_20H_NV (1 << 3)
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#define T_W 145 * 1000 /* NV register write time */
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#define T_RPH 35 /* Reset pulse hold time */
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#define T_SE 145 * 1000 /* Sector Erase Time */
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/* Page Erase 0xDB */
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#define JEDEC_PE 0xDB
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#define JEDEC_PE_OUTSIZE 0x04
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#define JEDEC_PE_INSIZE 0x00
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/* Read Status Register */
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#define JEDEC_RDSR 0x05
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#define JEDEC_RDSR_OUTSIZE 0x01
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#define JEDEC_RDSR_INSIZE 0x01
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/* Status Register Bits */
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#define SPI_SR_WIP (0x01 << 0)
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#define SPI_SR_WEL (0x01 << 1)
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#define SPI_SR_ERA_ERR (0x01 << 5)
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#define SPI_SR_AAI (0x01 << 6)
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/* Write Status Enable */
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#define JEDEC_EWSR 0x50
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#define JEDEC_EWSR_OUTSIZE 0x01
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#define JEDEC_EWSR_INSIZE 0x00
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/* Write Status Register */
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#define JEDEC_WRSR 0x01
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#define JEDEC_WRSR_OUTSIZE 0x02
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#define JEDEC_WRSR_INSIZE 0x00
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/* Enter 4-byte Address Mode */
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#define JEDEC_ENTER_4_BYTE_ADDR_MODE 0xB7
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/* Exit 4-byte Address Mode */
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#define JEDEC_EXIT_4_BYTE_ADDR_MODE 0xE9
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/* Write Extended Address Register */
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#define JEDEC_WRITE_EXT_ADDR_REG 0xC5
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/* Read Extended Address Register */
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#define JEDEC_READ_EXT_ADDR_REG 0xC8
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/* Read the memory */
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#define JEDEC_READ 0x03
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#define JEDEC_READ_OUTSIZE 0x04
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/* JEDEC_READ_INSIZE : any length */
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/* Read the memory (with delay after sending address) */
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#define JEDEC_READ_FAST 0x0b
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/* Write memory byte */
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#define JEDEC_BYTE_PROGRAM 0x02
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#define JEDEC_BYTE_PROGRAM_OUTSIZE 0x05
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#define JEDEC_BYTE_PROGRAM_INSIZE 0x00
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/* Write AAI word (SST25VF080B) */
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#define JEDEC_AAI_WORD_PROGRAM 0xad
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#define JEDEC_AAI_WORD_PROGRAM_OUTSIZE 0x06
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#define JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE 0x03
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#define JEDEC_AAI_WORD_PROGRAM_INSIZE 0x00
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/* Read the memory with 4-byte address
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From ANY mode (3-bytes or 4-bytes) it works with 4-byte address */
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#define JEDEC_READ_4BA 0x13
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/* Read the memory with 4-byte address (and delay after sending address)
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From ANY mode (3-bytes or 4-bytes) it works with 4-byte address */
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#define JEDEC_READ_4BA_FAST 0x0c
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/* Write memory byte with 4-byte address
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From ANY mode (3-bytes or 4-bytes) it works with 4-byte address */
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#define JEDEC_BYTE_PROGRAM_4BA 0x12
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/* Error codes */
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#define SPI_GENERIC_ERROR -1
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#define SPI_INVALID_OPCODE -2
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#define SPI_INVALID_ADDRESS -3
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#define SPI_INVALID_LENGTH -4
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#define SPI_FLASHROM_BUG -5
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#define SPI_PROGRAMMER_ERROR -6
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#endif /* !__SPI_H__ */
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