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b713d2e35c
Tested-by: Maciej Pijanka <maciej.pijanka@gmail.com> Corresponding to flashrom svn r1297. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Tested-by: Anton Kochkov <anton.kochkov@gmail.com> Acked-by: Anton Kochkov <anton.kochkov@gmail.com>
110 lines
3.4 KiB
C
110 lines
3.4 KiB
C
/*
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* This file is part of the flashrom project.
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*
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* Copyright (C) 2011 Carl-Daniel Hailfinger
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/* Datasheet: http://download.intel.com/design/network/datashts/82559_Fast_Ethernet_Multifunction_PCI_Cardbus_Controller_Datasheet.pdf */
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#include <stdlib.h>
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#include "flash.h"
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#include "programmer.h"
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uint8_t *nicintel_bar;
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uint8_t *nicintel_control_bar;
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const struct pcidev_status nics_intel[] = {
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{PCI_VENDOR_ID_INTEL, 0x1209, NT, "Intel", "8255xER/82551IT Fast Ethernet Controller"},
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{PCI_VENDOR_ID_INTEL, 0x1229, NT, "Intel", "82557/8/9/0/1 Ethernet Pro 100"},
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{},
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};
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/* Arbitrary limit, taken from the datasheet I just had lying around.
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* 128 kByte on the 82559 device. Or not. Depends on whom you ask.
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*/
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#define NICINTEL_MEMMAP_SIZE (128 * 1024)
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#define NICINTEL_MEMMAP_MASK (NICINTEL_MEMMAP_SIZE - 1)
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#define CSR_FCR 0x0c
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int nicintel_init(void)
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{
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uintptr_t addr;
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/* Needed only for PCI accesses on some platforms.
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* FIXME: Refactor that into get_mem_perms/get_io_perms/get_pci_perms?
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*/
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get_io_perms();
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/* No need to check for errors, pcidev_init() will not return in case
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* of errors.
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* FIXME: BAR2 is not available if the device uses the CardBus function.
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*/
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addr = pcidev_init(PCI_BASE_ADDRESS_2, nics_intel);
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nicintel_bar = physmap("Intel NIC flash", addr, NICINTEL_MEMMAP_SIZE);
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if (nicintel_bar == ERROR_PTR)
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goto error_out;
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/* FIXME: Using pcidev_dev _will_ cause pretty explosions in the future. */
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addr = pcidev_validate(pcidev_dev, PCI_BASE_ADDRESS_0, nics_intel);
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/* FIXME: This is not an aligned mapping. Use 4k? */
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nicintel_control_bar = physmap("Intel NIC control/status reg", addr, 0x10);
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if (nicintel_control_bar == ERROR_PTR)
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goto error_out;
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/* FIXME: This register is pretty undocumented in all publicly available
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* documentation from Intel. Let me quote the complete info we have:
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* "Flash Control Register: The Flash Control register allows the CPU to
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* enable writes to an external Flash. The Flash Control Register is a
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* 32-bit field that allows access to an external Flash device."
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* Ah yes, we also know where it is, but we have absolutely _no_ idea
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* what we should do with it. Write 0x0001 because we have nothing
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* better to do with our time.
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*/
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pci_rmmio_writew(0x0001, nicintel_control_bar + CSR_FCR);
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buses_supported = CHIP_BUSTYPE_PARALLEL;
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max_rom_decode.parallel = NICINTEL_MEMMAP_SIZE;
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return 0;
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error_out:
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pci_cleanup(pacc);
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release_io_perms();
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return 1;
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}
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int nicintel_shutdown(void)
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{
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physunmap(nicintel_bar, NICINTEL_MEMMAP_SIZE);
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pci_cleanup(pacc);
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release_io_perms();
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return 0;
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}
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void nicintel_chip_writeb(uint8_t val, chipaddr addr)
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{
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pci_mmio_writeb(val, nicintel_bar + (addr & NICINTEL_MEMMAP_MASK));
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}
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uint8_t nicintel_chip_readb(const chipaddr addr)
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{
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return pci_mmio_readb(nicintel_bar + (addr & NICINTEL_MEMMAP_MASK));
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}
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