mirror of
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5561955b11
Previously the internal programmer used its own code to initialize pcilib. This patch extracts the common code from the internal programmer and pcidev_init() into pcidev_init_common(). This fixes the non-existent PCI cleanup of the internal programmer and adds an additional safety by checking for an already existing PCI context. We got a nice shutdown function registration infrastructure, but did not use it very wisely. Instead we added shutdown functions to a myriad of programmers unnecessarily. In this patch we get rid of those that do only call pci_cleanup(pacc) by adding a shutdown function the pcidev.c itself that gets registered by pcidev_init(). Corresponding to flashrom svn r1642. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
141 lines
4.5 KiB
C
141 lines
4.5 KiB
C
/*
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* This file is part of the flashrom project.
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*
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* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#if defined(__i386__) || defined(__x86_64__)
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#include <stdlib.h>
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#include "flash.h"
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#include "programmer.h"
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#include "hwaccess.h"
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#define BIOS_ROM_ADDR 0x04
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#define BIOS_ROM_DATA 0x08
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#define INT_STATUS 0x0e
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#define INTERNAL_CONFIG 0x00
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#define SELECT_REG_WINDOW 0x800
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#define PCI_VENDOR_ID_3COM 0x10b7
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static uint32_t internal_conf;
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static uint16_t id;
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const struct dev_entry nics_3com[] = {
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/* 3C90xB */
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{0x10b7, 0x9055, OK, "3COM", "3C90xB: PCI 10/100 Mbps; shared 10BASE-T/100BASE-TX"},
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{0x10b7, 0x9001, NT, "3COM", "3C90xB: PCI 10/100 Mbps; shared 10BASE-T/100BASE-T4" },
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{0x10b7, 0x9004, OK, "3COM", "3C90xB: PCI 10BASE-T (TPO)" },
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{0x10b7, 0x9005, NT, "3COM", "3C90xB: PCI 10BASE-T/10BASE2/AUI (COMBO)" },
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{0x10b7, 0x9006, NT, "3COM", "3C90xB: PCI 10BASE-T/10BASE2 (TPC)" },
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{0x10b7, 0x900a, NT, "3COM", "3C90xB: PCI 10BASE-FL" },
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{0x10b7, 0x905a, NT, "3COM", "3C90xB: PCI 10BASE-FX" },
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{0x10b7, 0x9058, OK, "3COM", "3C905B: Cyclone 10/100/BNC" },
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/* 3C905C */
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{0x10b7, 0x9200, OK, "3COM", "3C905C: EtherLink 10/100 PCI (TX)" },
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/* 3C980C */
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{0x10b7, 0x9805, NT, "3COM", "3C980C: EtherLink Server 10/100 PCI (TX)" },
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{0},
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};
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static void nic3com_chip_writeb(const struct flashctx *flash, uint8_t val,
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chipaddr addr);
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static uint8_t nic3com_chip_readb(const struct flashctx *flash,
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const chipaddr addr);
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static const struct par_programmer par_programmer_nic3com = {
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.chip_readb = nic3com_chip_readb,
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.chip_readw = fallback_chip_readw,
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.chip_readl = fallback_chip_readl,
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.chip_readn = fallback_chip_readn,
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.chip_writeb = nic3com_chip_writeb,
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.chip_writew = fallback_chip_writew,
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.chip_writel = fallback_chip_writel,
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.chip_writen = fallback_chip_writen,
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};
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static int nic3com_shutdown(void *data)
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{
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/* 3COM 3C90xB cards need a special fixup. */
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if (id == 0x9055 || id == 0x9001 || id == 0x9004 || id == 0x9005
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|| id == 0x9006 || id == 0x900a || id == 0x905a || id == 0x9058) {
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/* Select register window 3 and restore the receiver status. */
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OUTW(SELECT_REG_WINDOW + 3, io_base_addr + INT_STATUS);
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OUTL(internal_conf, io_base_addr + INTERNAL_CONFIG);
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}
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return 0;
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}
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int nic3com_init(void)
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{
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if (rget_io_perms())
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return 1;
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/* No need to check for errors, pcidev_init() will not return in case of errors. */
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io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_3com);
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id = pcidev_dev->device_id;
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/* 3COM 3C90xB cards need a special fixup. */
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if (id == 0x9055 || id == 0x9001 || id == 0x9004 || id == 0x9005
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|| id == 0x9006 || id == 0x900a || id == 0x905a || id == 0x9058) {
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/* Select register window 3 and save the receiver status. */
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OUTW(SELECT_REG_WINDOW + 3, io_base_addr + INT_STATUS);
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internal_conf = INL(io_base_addr + INTERNAL_CONFIG);
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/* Set receiver type to MII for full BIOS ROM access. */
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OUTL((internal_conf & 0xf00fffff) | 0x00600000, io_base_addr);
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}
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/*
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* The lowest 16 bytes of the I/O mapped register space of (most) 3COM
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* cards form a 'register window' into one of multiple (usually 8)
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* register banks. For 3C90xB/3C90xC we need register window/bank 0.
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*/
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OUTW(SELECT_REG_WINDOW + 0, io_base_addr + INT_STATUS);
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if (register_shutdown(nic3com_shutdown, NULL))
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return 1;
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max_rom_decode.parallel = 128 * 1024;
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register_par_programmer(&par_programmer_nic3com, BUS_PARALLEL);
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return 0;
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}
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static void nic3com_chip_writeb(const struct flashctx *flash, uint8_t val,
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chipaddr addr)
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{
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OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR);
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OUTB(val, io_base_addr + BIOS_ROM_DATA);
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}
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static uint8_t nic3com_chip_readb(const struct flashctx *flash,
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const chipaddr addr)
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{
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OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR);
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return INB(io_base_addr + BIOS_ROM_DATA);
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}
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#else
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#error PCI port I/O access is not supported on this architecture yet.
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#endif
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