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cceafa2ad0
- x86/x86_64 (little endian) - PowerPC (big endian) - MIPS (big+little endian) No changes to programmer specific code. This means any drivers with MMIO access will _not_ suddenly start working on big endian systems, but with this patch everything is in place to fix them. Compilation should work on all architectures listed above for all drivers except nic3com and nicrealtek which require PCI Port IO which is x86-only for now. To compile without nic3com and nicrealtek, run make distclean make CONFIG_NIC3COM=no CONFIG_NICREALTEK=no Thanks to Misha Manulis for testing early versions of this patch on PowerPC (big endian) with the satasii programmer. Thanks to Segher Boessenkool for design review and for helping out with compiler tricks and pointing out that we need eieio on PowerPC. Thanks to Vladimir Serbinenko for compile testing on MIPS (little endian) and PowerPC (big endian) and for runtime testing on MIPS (little endian). Thanks to David Daney for compile testing on MIPS (big endian). Thanks to Uwe Hermann for compile and runtime testing on x86_64. DO NOT RUN flashrom ON NON-X86 AFTER APPLYING THIS PATCH! This patch only provides the infrastructure, but does not convert any drivers, so flashrom will compile, but it won't do the right thing on non-x86 platforms. Corresponding to flashrom svn r1013. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Misha Manulis <misha@manulis.com> Acked-by: Vladimir 'phcoder/φ-coder' Serbinenko <phcoder@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Segher Boessenkool <segher@kernel.crashing.org>
121 lines
3.7 KiB
C
121 lines
3.7 KiB
C
/*
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* This file is part of the flashrom project.
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*
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* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#if defined(__i386__) || defined(__x86_64__)
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#include <stdlib.h>
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#include <string.h>
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#include <sys/types.h>
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#include "flash.h"
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#define BIOS_ROM_ADDR 0x04
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#define BIOS_ROM_DATA 0x08
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#define INT_STATUS 0x0e
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#define INTERNAL_CONFIG 0x00
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#define SELECT_REG_WINDOW 0x800
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#define PCI_VENDOR_ID_3COM 0x10b7
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uint32_t internal_conf;
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uint16_t id;
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struct pcidev_status nics_3com[] = {
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/* 3C90xB */
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{0x10b7, 0x9055, OK, "3COM", "3C90xB: PCI 10/100 Mbps; shared 10BASE-T/100BASE-TX"},
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{0x10b7, 0x9001, NT, "3COM", "3C90xB: PCI 10/100 Mbps; shared 10BASE-T/100BASE-T4" },
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{0x10b7, 0x9004, OK, "3COM", "3C90xB: PCI 10BASE-T (TPO)" },
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{0x10b7, 0x9005, NT, "3COM", "3C90xB: PCI 10BASE-T/10BASE2/AUI (COMBO)" },
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{0x10b7, 0x9006, NT, "3COM", "3C90xB: PCI 10BASE-T/10BASE2 (TPC)" },
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{0x10b7, 0x900a, NT, "3COM", "3C90xB: PCI 10BASE-FL" },
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{0x10b7, 0x905a, NT, "3COM", "3C90xB: PCI 10BASE-FX" },
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{0x10b7, 0x9058, OK, "3COM", "3C905B: Cyclone 10/100/BNC" },
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/* 3C905C */
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{0x10b7, 0x9200, OK, "3COM", "3C905C: EtherLink 10/100 PCI (TX)" },
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/* 3C980C */
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{0x10b7, 0x9805, NT, "3COM", "3C980C: EtherLink Server 10/100 PCI (TX)" },
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{},
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};
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int nic3com_init(void)
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{
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get_io_perms();
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io_base_addr = pcidev_init(PCI_VENDOR_ID_3COM, PCI_BASE_ADDRESS_0,
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nics_3com, programmer_param);
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id = pcidev_dev->device_id;
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/* 3COM 3C90xB cards need a special fixup. */
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if (id == 0x9055 || id == 0x9001 || id == 0x9004 || id == 0x9005
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|| id == 0x9006 || id == 0x900a || id == 0x905a || id == 0x9058) {
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/* Select register window 3 and save the receiver status. */
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OUTW(SELECT_REG_WINDOW + 3, io_base_addr + INT_STATUS);
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internal_conf = INL(io_base_addr + INTERNAL_CONFIG);
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/* Set receiver type to MII for full BIOS ROM access. */
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OUTL((internal_conf & 0xf00fffff) | 0x00600000, io_base_addr);
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}
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/*
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* The lowest 16 bytes of the I/O mapped register space of (most) 3COM
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* cards form a 'register window' into one of multiple (usually 8)
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* register banks. For 3C90xB/3C90xC we need register window/bank 0.
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*/
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OUTW(SELECT_REG_WINDOW + 0, io_base_addr + INT_STATUS);
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buses_supported = CHIP_BUSTYPE_PARALLEL;
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return 0;
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}
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int nic3com_shutdown(void)
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{
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/* 3COM 3C90xB cards need a special fixup. */
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if (id == 0x9055 || id == 0x9001 || id == 0x9004 || id == 0x9005
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|| id == 0x9006 || id == 0x900a || id == 0x905a || id == 0x9058) {
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/* Select register window 3 and restore the receiver status. */
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OUTW(SELECT_REG_WINDOW + 3, io_base_addr + INT_STATUS);
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OUTL(internal_conf, io_base_addr + INTERNAL_CONFIG);
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}
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free(programmer_param);
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pci_cleanup(pacc);
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release_io_perms();
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return 0;
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}
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void nic3com_chip_writeb(uint8_t val, chipaddr addr)
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{
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OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR);
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OUTB(val, io_base_addr + BIOS_ROM_DATA);
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}
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uint8_t nic3com_chip_readb(const chipaddr addr)
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{
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OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR);
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return INB(io_base_addr + BIOS_ROM_DATA);
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}
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#else
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#error PCI port I/O access is not supported on this architecture yet.
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#endif
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