mirror of
https://review.coreboot.org/flashrom.git
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a2faddf7d3
Pcidev_init() now returns struct pci_device * instead of a BAR stored in PCI config space. This allows for real error checking instead of having exit(1) everywhere in pcidev.c. Thanks to Niklas Söderlund for coming up with the original error handling patch which was slightly modified and folded into this patch. Move the declaration of struct pci_device in programmer.h before the first user. Corresponding to flashrom svn r1644. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
136 lines
3.8 KiB
C
136 lines
3.8 KiB
C
/*
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* This file is part of the flashrom project.
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*
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* Copyright (C) 2009 Joerg Fischer <turboj@gmx.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#if defined(__i386__) || defined(__x86_64__)
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#include <stdlib.h>
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#include "flash.h"
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#include "programmer.h"
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#include "hwaccess.h"
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#define PCI_VENDOR_ID_REALTEK 0x10ec
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#define PCI_VENDOR_ID_SMC1211 0x1113
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static int bios_rom_addr, bios_rom_data;
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const struct dev_entry nics_realtek[] = {
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{0x10ec, 0x8139, OK, "Realtek", "RTL8139/8139C/8139C+"},
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{0x10ec, 0x8169, NT, "Realtek", "RTL8169"},
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{0x1113, 0x1211, OK, "SMC", "1211TX"}, /* RTL8139 clone */
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{0},
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};
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static void nicrealtek_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr);
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static uint8_t nicrealtek_chip_readb(const struct flashctx *flash, const chipaddr addr);
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static const struct par_programmer par_programmer_nicrealtek = {
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.chip_readb = nicrealtek_chip_readb,
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.chip_readw = fallback_chip_readw,
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.chip_readl = fallback_chip_readl,
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.chip_readn = fallback_chip_readn,
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.chip_writeb = nicrealtek_chip_writeb,
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.chip_writew = fallback_chip_writew,
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.chip_writel = fallback_chip_writel,
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.chip_writen = fallback_chip_writen,
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};
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static int nicrealtek_shutdown(void *data)
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{
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/* FIXME: We forgot to disable software access again. */
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return 0;
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}
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int nicrealtek_init(void)
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{
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struct pci_dev *dev = NULL;
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if (rget_io_perms())
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return 1;
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dev = pcidev_init(nics_realtek, PCI_BASE_ADDRESS_0);
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if (!dev)
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return 1;
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io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0);
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/* Beware, this ignores the vendor ID! */
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switch (dev->device_id) {
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case 0x8139: /* RTL8139 */
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case 0x1211: /* SMC 1211TX */
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default:
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bios_rom_addr = 0xD4;
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bios_rom_data = 0xD7;
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break;
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case 0x8169: /* RTL8169 */
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bios_rom_addr = 0x30;
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bios_rom_data = 0x33;
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break;
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}
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if (register_shutdown(nicrealtek_shutdown, NULL))
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return 1;
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register_par_programmer(&par_programmer_nicrealtek, BUS_PARALLEL);
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return 0;
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}
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static void nicrealtek_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr)
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{
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/* Output addr and data, set WE to 0, set OE to 1, set CS to 0,
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* enable software access.
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*/
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OUTL(((uint32_t)addr & 0x01FFFF) | 0x0A0000 | (val << 24),
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io_base_addr + bios_rom_addr);
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/* Output addr and data, set WE to 1, set OE to 1, set CS to 1,
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* enable software access.
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*/
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OUTL(((uint32_t)addr & 0x01FFFF) | 0x1E0000 | (val << 24),
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io_base_addr + bios_rom_addr);
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}
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static uint8_t nicrealtek_chip_readb(const struct flashctx *flash, const chipaddr addr)
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{
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uint8_t val;
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/* FIXME: Can we skip reading the old data and simply use 0? */
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/* Read old data. */
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val = INB(io_base_addr + bios_rom_data);
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/* Output new addr and old data, set WE to 1, set OE to 0, set CS to 0,
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* enable software access.
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*/
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OUTL(((uint32_t)addr & 0x01FFFF) | 0x060000 | (val << 24),
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io_base_addr + bios_rom_addr);
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/* Read new data. */
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val = INB(io_base_addr + bios_rom_data);
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/* Output addr and new data, set WE to 1, set OE to 1, set CS to 1,
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* enable software access.
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*/
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OUTL(((uint32_t)addr & 0x01FFFF) | 0x1E0000 | (val << 24),
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io_base_addr + bios_rom_addr);
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return val;
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}
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#else
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#error PCI port I/O access is not supported on this architecture yet.
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#endif
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