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The page on wiki is here: https://wiki.flashrom.org/ISP Change-Id: If4752f0f02ae973b3d832f42166de643d95c9f97 Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/83451 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alexander Goncharov <chat@joursoir.net>
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2.4 KiB
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46 lines
2.4 KiB
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=====================
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In-System Programming
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=====================
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**In-System Programming** (ISP) sometimes also called **in situ programming** is used to describe
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the procedure of writing a flash chip while it is (already/still) attached to the circuit
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it is to be used with. Of course any normal "BIOS flash" procedure is a kind of ISP
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but when we refer to ISP we usually mean something different: programming a flash chip by external means
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while it is mounted on a motherboard.
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This is usually done with SPI chips only. Some mainboards have a special header for this
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(often named "ISP", "ISP1", or "SPI") and there should be no problem with accessing the chip
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then as long as the wires are not too long.
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If there is no special header then using a special SO(IC) clip is an easy and reliable way
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to attach an external programmer. They are produced by different vendors (e.g. Pomona, 3M)
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and are available from many distributors (e.g. Distrelec) for 20-50$/€.
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Problems
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========
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* Check the other potential problems (:doc:`misc_notes`) with other types of programming setups first.
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* The SPI bus is not isolated enough. Often parts of the chipset are powered on partially
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(by the voltage supplied via the Vcc pin of the flash chip). In that case
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disconnect Vcc from the programmer and power it with its normal PSU and:
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* Try powering up the board normally and holding it in reset (e.g. use a jumper instead of the reset push button).
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* Some chipsets (e.g. Intel ICHs/PCHs) have edge triggered resets. In this case holding them in reset will not work.
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This is especially a problem with Intel chipsets because they contain an EC (named ME by Intel, see :doc:`management_engine`),
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which uses the flash (r/w!). In this case you can trigger the reset line in short intervals.
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For example by connecting it to the chip select (CS) line of the SPI bus or a dedicated clock signal from the programmer.
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This should not be too fast though! Reset lines usually require pulses with a minimum duration.
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* On some boards, you can try disconnecting the ATX12V header (yellow/black wires only) from the motherboard,
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or even remove the CPU or RAM - if the programmer supports SPI sniffing, you may be able to verify that the there is no SPI traffic.
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Images
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========
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Pomona 8-pin SOIC clip with attached jumper wires.
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.. image:: Pomona_5250_soic8.jpg
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A cheap, but very fragile alternative: DIP socket as clip
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.. image:: 1200px-DIP_socket_as_SOIC_clip.jpg
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