mirror of
https://review.coreboot.org/flashrom.git
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6697f71ade
Tested mainboards: OK: - ASUS F2A85-M Reported by various corebooters - ASUS M2N-MX SE Plus Reported by Antonio - ASUS P5LD2 Reported by François Revol - Lenovo ThinkPad T530 Reported and partially authored by Edward O'Callaghan - MSI MS-7502 (Medion MD8833) Reported by naq on IRC - Shuttle AB61 Reported by olofolleola4 - ZOTAC IONITX-F-E Reported by Bernardo Kuri Flash chips: - Atmel AT45DB021D to PREW (+PREW) Reported by The Raven - Atmel AT25F4096 to PREW (+PREW) Reported by 공준혁 - GigaDevice GD25Q16(B) to PREW (+PREW) Reported by luxflow@live.com using a GD25Q16BSIG - Catalyst CAT28F512 Mark erase and write as known bad (not implemented) Miscellaneous: - Various spelling corrections by Daniele Forsi. - Added and refined a bunch of chips originally investigated by Carl-Daniel. - Marked the ARM-USB-OCD-H programmer as tested (reported by Ruud Schramp). - Tiny other stuff. Corresponding to flashrom svn r1839. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
87 lines
2.7 KiB
C
87 lines
2.7 KiB
C
/*
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* This file is part of the flashrom project.
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*
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* Copyright (C) 2011 Carl-Daniel Hailfinger
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* Copyright (C) 2012 Kyösti Mälkki <kyosti.malkki@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <stdlib.h>
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#include "flash.h"
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#include "programmer.h"
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#include "hwaccess.h"
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static uint8_t *it8212_bar = NULL;
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#define PCI_VENDOR_ID_ITE 0x1283
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const struct dev_entry devs_it8212[] = {
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{PCI_VENDOR_ID_ITE, 0x8212, NT, "ITE", "8212F PATA RAID"},
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{},
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};
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#define IT8212_MEMMAP_SIZE (128 * 1024)
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#define IT8212_MEMMAP_MASK (IT8212_MEMMAP_SIZE - 1)
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static void it8212_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr);
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static uint8_t it8212_chip_readb(const struct flashctx *flash, const chipaddr addr);
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static const struct par_master par_master_it8212 = {
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.chip_readb = it8212_chip_readb,
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.chip_readw = fallback_chip_readw,
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.chip_readl = fallback_chip_readl,
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.chip_readn = fallback_chip_readn,
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.chip_writeb = it8212_chip_writeb,
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.chip_writew = fallback_chip_writew,
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.chip_writel = fallback_chip_writel,
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.chip_writen = fallback_chip_writen,
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};
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int it8212_init(void)
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{
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if (rget_io_perms())
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return 1;
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struct pci_dev *dev = pcidev_init(devs_it8212, PCI_ROM_ADDRESS);
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if (!dev)
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return 1;
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/* Bit 0 is address decode enable, 17-31 the base address, everything else reserved/zero. */
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uint32_t io_base_addr = pcidev_readbar(dev, PCI_ROM_ADDRESS) & 0xFFFFFFFE;
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if (!io_base_addr)
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return 1;
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it8212_bar = rphysmap("IT8212F flash", io_base_addr, IT8212_MEMMAP_SIZE);
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if (it8212_bar == ERROR_PTR)
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return 1;
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/* Restore ROM BAR decode state automatically at shutdown. */
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rpci_write_long(dev, PCI_ROM_ADDRESS, io_base_addr | 0x01);
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max_rom_decode.parallel = IT8212_MEMMAP_SIZE;
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register_par_master(&par_master_it8212, BUS_PARALLEL);
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return 0;
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}
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static void it8212_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr)
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{
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pci_mmio_writeb(val, it8212_bar + (addr & IT8212_MEMMAP_MASK));
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}
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static uint8_t it8212_chip_readb(const struct flashctx *flash, const chipaddr addr)
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{
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return pci_mmio_readb(it8212_bar + (addr & IT8212_MEMMAP_MASK));
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}
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