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mirror of https://review.coreboot.org/flashrom.git synced 2025-04-27 07:02:34 +02:00
flashrom/spi.c
Edward O'Callaghan e4ddc36371 const'ify flashctx to align signatures with cros flashrom
The ChromiumOS flashrom fork has since const'ify flashctx
in a few places. This aligns the function signatures to
match with downstream to ease forward porting patches
out of downstream back into mainline flashrom.

This patch is minimum viable alignment and so feedback is
welcome.

Change-Id: Iff6dbda13cb0d941481c0d204b9c30895630fbd1
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/40324
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-30 08:00:41 +00:00

153 lines
4.4 KiB
C

/*
* This file is part of the flashrom project.
*
* Copyright (C) 2007, 2008, 2009, 2010, 2011 Carl-Daniel Hailfinger
* Copyright (C) 2008 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/*
* Contains the generic SPI framework
*/
#include <strings.h>
#include <string.h>
#include "flash.h"
#include "flashchips.h"
#include "chipdrivers.h"
#include "programmer.h"
#include "spi.h"
int spi_send_command(const struct flashctx *flash, unsigned int writecnt,
unsigned int readcnt, const unsigned char *writearr,
unsigned char *readarr)
{
return flash->mst->spi.command(flash, writecnt, readcnt, writearr,
readarr);
}
int spi_send_multicommand(const struct flashctx *flash, struct spi_command *cmds)
{
return flash->mst->spi.multicommand(flash, cmds);
}
int default_spi_send_command(const struct flashctx *flash, unsigned int writecnt,
unsigned int readcnt,
const unsigned char *writearr,
unsigned char *readarr)
{
struct spi_command cmd[] = {
{
.writecnt = writecnt,
.readcnt = readcnt,
.writearr = writearr,
.readarr = readarr,
}, {
.writecnt = 0,
.writearr = NULL,
.readcnt = 0,
.readarr = NULL,
}};
return spi_send_multicommand(flash, cmd);
}
int default_spi_send_multicommand(const struct flashctx *flash,
struct spi_command *cmds)
{
int result = 0;
for (; (cmds->writecnt || cmds->readcnt) && !result; cmds++) {
result = spi_send_command(flash, cmds->writecnt, cmds->readcnt,
cmds->writearr, cmds->readarr);
}
return result;
}
int default_spi_read(struct flashctx *flash, uint8_t *buf, unsigned int start,
unsigned int len)
{
unsigned int max_data = flash->mst->spi.max_data_read;
if (max_data == MAX_DATA_UNSPECIFIED) {
msg_perr("%s called, but SPI read chunk size not defined "
"on this hardware. Please report a bug at "
"flashrom@flashrom.org\n", __func__);
return 1;
}
return spi_read_chunked(flash, buf, start, len, max_data);
}
int default_spi_write_256(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len)
{
unsigned int max_data = flash->mst->spi.max_data_write;
if (max_data == MAX_DATA_UNSPECIFIED) {
msg_perr("%s called, but SPI write chunk size not defined "
"on this hardware. Please report a bug at "
"flashrom@flashrom.org\n", __func__);
return 1;
}
return spi_write_chunked(flash, buf, start, len, max_data);
}
int spi_chip_read(struct flashctx *flash, uint8_t *buf, unsigned int start,
unsigned int len)
{
int ret;
size_t to_read;
for (; len; len -= to_read, buf += to_read, start += to_read) {
/* Do not cross 16MiB boundaries in a single transfer.
This helps with
o multi-die 4-byte-addressing chips,
o dediprog that has a protocol limit of 32MiB-512B. */
to_read = min(ALIGN_DOWN(start + 16*MiB, 16*MiB) - start, len);
ret = flash->mst->spi.read(flash, buf, start, to_read);
if (ret)
return ret;
}
return 0;
}
/*
* Program chip using page (256 bytes) programming.
* Some SPI masters can't do this, they use single byte programming instead.
* The redirect to single byte programming is achieved by setting
* .write_256 = spi_chip_write_1
*/
/* real chunksize is up to 256, logical chunksize is 256 */
int spi_chip_write_256(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len)
{
return flash->mst->spi.write_256(flash, buf, start, len);
}
int spi_aai_write(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len)
{
return flash->mst->spi.write_aai(flash, buf, start, len);
}
int register_spi_master(const struct spi_master *mst)
{
struct registered_master rmst;
if (!mst->write_aai || !mst->write_256 || !mst->read || !mst->command ||
!mst->multicommand ||
((mst->command == default_spi_send_command) &&
(mst->multicommand == default_spi_send_multicommand))) {
msg_perr("%s called with incomplete master definition. "
"Please report a bug at flashrom@flashrom.org\n",
__func__);
return ERROR_FLASHROM_BUG;
}
rmst.buses_supported = BUS_SPI;
rmst.spi = *mst;
return register_master(&rmst);
}