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Get rid of the layering violations around ICH's BBAR. Move all the weird address handling into (surprise, surprise) `ichspi.c`. Might fix writes for the `BBAR != 0` case by accident. Background: Some ICHs have a BBAR (BIOS Base Address Configuration Register) that, if set, limits the valid address range to [BBAR, 2^24). Current code lifted addresses for REMS, RES and READ operations by BBAR, now we do it for all addresses in ichspi. Special care has to be taken if the BBAR is not aligned by the flash chip's size. In this case, the lower part of the chip (from BBAR aligned down, up to BBAR) is inacces- sible (this seems to be the original intend behind BBAR) and has to be left out in the address offset calculation. Change-Id: Icbac513c5339e8aff624870252133284ef85ab73 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/22396 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
145 lines
4.3 KiB
C
145 lines
4.3 KiB
C
/*
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* This file is part of the flashrom project.
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*
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* Copyright (C) 2007, 2008, 2009, 2010, 2011 Carl-Daniel Hailfinger
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* Copyright (C) 2008 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/*
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* Contains the generic SPI framework
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*/
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#include <strings.h>
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#include <string.h>
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#include "flash.h"
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#include "flashchips.h"
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#include "chipdrivers.h"
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#include "programmer.h"
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#include "spi.h"
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int spi_send_command(struct flashctx *flash, unsigned int writecnt,
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unsigned int readcnt, const unsigned char *writearr,
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unsigned char *readarr)
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{
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return flash->mst->spi.command(flash, writecnt, readcnt, writearr,
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readarr);
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}
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int spi_send_multicommand(struct flashctx *flash, struct spi_command *cmds)
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{
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return flash->mst->spi.multicommand(flash, cmds);
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}
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int default_spi_send_command(struct flashctx *flash, unsigned int writecnt,
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unsigned int readcnt,
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const unsigned char *writearr,
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unsigned char *readarr)
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{
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struct spi_command cmd[] = {
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{
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.writecnt = writecnt,
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.readcnt = readcnt,
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.writearr = writearr,
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.readarr = readarr,
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}, {
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.writecnt = 0,
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.writearr = NULL,
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.readcnt = 0,
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.readarr = NULL,
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}};
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return spi_send_multicommand(flash, cmd);
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}
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int default_spi_send_multicommand(struct flashctx *flash,
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struct spi_command *cmds)
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{
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int result = 0;
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for (; (cmds->writecnt || cmds->readcnt) && !result; cmds++) {
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result = spi_send_command(flash, cmds->writecnt, cmds->readcnt,
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cmds->writearr, cmds->readarr);
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}
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return result;
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}
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int default_spi_read(struct flashctx *flash, uint8_t *buf, unsigned int start,
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unsigned int len)
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{
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unsigned int max_data = flash->mst->spi.max_data_read;
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if (max_data == MAX_DATA_UNSPECIFIED) {
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msg_perr("%s called, but SPI read chunk size not defined "
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"on this hardware. Please report a bug at "
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"flashrom@flashrom.org\n", __func__);
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return 1;
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}
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return spi_read_chunked(flash, buf, start, len, max_data);
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}
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int default_spi_write_256(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len)
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{
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unsigned int max_data = flash->mst->spi.max_data_write;
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if (max_data == MAX_DATA_UNSPECIFIED) {
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msg_perr("%s called, but SPI write chunk size not defined "
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"on this hardware. Please report a bug at "
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"flashrom@flashrom.org\n", __func__);
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return 1;
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}
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return spi_write_chunked(flash, buf, start, len, max_data);
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}
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int spi_chip_read(struct flashctx *flash, uint8_t *buf, unsigned int start,
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unsigned int len)
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{
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return flash->mst->spi.read(flash, buf, start, len);
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}
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/*
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* Program chip using page (256 bytes) programming.
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* Some SPI masters can't do this, they use single byte programming instead.
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* The redirect to single byte programming is achieved by setting
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* .write_256 = spi_chip_write_1
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*/
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/* real chunksize is up to 256, logical chunksize is 256 */
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int spi_chip_write_256(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len)
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{
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return flash->mst->spi.write_256(flash, buf, start, len);
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}
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int spi_aai_write(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len)
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{
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return flash->mst->spi.write_aai(flash, buf, start, len);
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}
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int register_spi_master(const struct spi_master *mst)
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{
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struct registered_master rmst;
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if (!mst->write_aai || !mst->write_256 || !mst->read || !mst->command ||
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!mst->multicommand ||
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((mst->command == default_spi_send_command) &&
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(mst->multicommand == default_spi_send_multicommand))) {
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msg_perr("%s called with incomplete master definition. "
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"Please report a bug at flashrom@flashrom.org\n",
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__func__);
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return ERROR_FLASHROM_BUG;
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}
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rmst.buses_supported = BUS_SPI;
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rmst.spi = *mst;
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return register_master(&rmst);
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}
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