mirror of
https://review.coreboot.org/flashrom.git
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a2faddf7d3
Pcidev_init() now returns struct pci_device * instead of a BAR stored in PCI config space. This allows for real error checking instead of having exit(1) everywhere in pcidev.c. Thanks to Niklas Söderlund for coming up with the original error handling patch which was slightly modified and folded into this patch. Move the declaration of struct pci_device in programmer.h before the first user. Corresponding to flashrom svn r1644. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
130 lines
4.1 KiB
C
130 lines
4.1 KiB
C
/*
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* This file is part of the flashrom project.
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*
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* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <stdlib.h>
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#include <string.h>
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#include "flash.h"
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#include "programmer.h"
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#include "hwaccess.h"
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#define PCI_VENDOR_ID_NVIDIA 0x10de
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/* Mask to restrict flash accesses to a 128kB memory window.
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* FIXME: Is this size a one-fits-all or card dependent?
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*/
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#define GFXNVIDIA_MEMMAP_MASK ((1 << 17) - 1)
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#define GFXNVIDIA_MEMMAP_SIZE (16 * 1024 * 1024)
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uint8_t *nvidia_bar;
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const struct dev_entry gfx_nvidia[] = {
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{0x10de, 0x0010, NT, "NVIDIA", "Mutara V08 [NV2]" },
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{0x10de, 0x0018, NT, "NVIDIA", "RIVA 128" },
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{0x10de, 0x0020, NT, "NVIDIA", "RIVA TNT" },
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{0x10de, 0x0028, NT, "NVIDIA", "RIVA TNT2/TNT2 Pro" },
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{0x10de, 0x0029, NT, "NVIDIA", "RIVA TNT2 Ultra" },
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{0x10de, 0x002c, NT, "NVIDIA", "Vanta/Vanta LT" },
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{0x10de, 0x002d, OK, "NVIDIA", "RIVA TNT2 Model 64/Model 64 Pro" },
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{0x10de, 0x00a0, NT, "NVIDIA", "Aladdin TNT2" },
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{0x10de, 0x0100, NT, "NVIDIA", "GeForce 256" },
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{0x10de, 0x0101, NT, "NVIDIA", "GeForce DDR" },
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{0x10de, 0x0103, NT, "NVIDIA", "Quadro" },
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{0x10de, 0x0110, NT, "NVIDIA", "GeForce2 MX" },
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{0x10de, 0x0111, NT, "NVIDIA", "GeForce2 MX" },
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{0x10de, 0x0112, NT, "NVIDIA", "GeForce2 GO" },
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{0x10de, 0x0113, NT, "NVIDIA", "Quadro2 MXR" },
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{0x10de, 0x0150, NT, "NVIDIA", "GeForce2 GTS/Pro" },
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{0x10de, 0x0151, NT, "NVIDIA", "GeForce2 GTS" },
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{0x10de, 0x0152, NT, "NVIDIA", "GeForce2 Ultra" },
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{0x10de, 0x0153, NT, "NVIDIA", "Quadro2 Pro" },
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{0x10de, 0x0200, NT, "NVIDIA", "GeForce 3 nFX" },
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{0x10de, 0x0201, NT, "NVIDIA", "GeForce 3 nFX" },
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{0x10de, 0x0202, NT, "NVIDIA", "GeForce 3 nFX Ultra" },
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{0x10de, 0x0203, NT, "NVIDIA", "Quadro 3 DDC" },
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{0},
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};
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static void gfxnvidia_chip_writeb(const struct flashctx *flash, uint8_t val,
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chipaddr addr);
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static uint8_t gfxnvidia_chip_readb(const struct flashctx *flash,
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const chipaddr addr);
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static const struct par_programmer par_programmer_gfxnvidia = {
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.chip_readb = gfxnvidia_chip_readb,
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.chip_readw = fallback_chip_readw,
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.chip_readl = fallback_chip_readl,
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.chip_readn = fallback_chip_readn,
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.chip_writeb = gfxnvidia_chip_writeb,
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.chip_writew = fallback_chip_writew,
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.chip_writel = fallback_chip_writel,
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.chip_writen = fallback_chip_writen,
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};
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static int gfxnvidia_shutdown(void *data)
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{
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physunmap(nvidia_bar, GFXNVIDIA_MEMMAP_SIZE);
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return 0;
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}
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int gfxnvidia_init(void)
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{
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struct pci_dev *dev = NULL;
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uint32_t reg32;
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if (rget_io_perms())
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return 1;
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dev = pcidev_init(gfx_nvidia, PCI_BASE_ADDRESS_0);
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if (!dev)
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return 1;
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io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0);
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io_base_addr += 0x300000;
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msg_pinfo("Detected NVIDIA I/O base address: 0x%x.\n", io_base_addr);
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nvidia_bar = physmap("NVIDIA", io_base_addr, GFXNVIDIA_MEMMAP_SIZE);
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if (register_shutdown(gfxnvidia_shutdown, NULL))
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return 1;
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/* Allow access to flash interface (will disable screen). */
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reg32 = pci_read_long(dev, 0x50);
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reg32 &= ~(1 << 0);
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rpci_write_long(dev, 0x50, reg32);
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/* Write/erase doesn't work. */
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programmer_may_write = 0;
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register_par_programmer(&par_programmer_gfxnvidia, BUS_PARALLEL);
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return 0;
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}
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static void gfxnvidia_chip_writeb(const struct flashctx *flash, uint8_t val,
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chipaddr addr)
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{
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pci_mmio_writeb(val, nvidia_bar + (addr & GFXNVIDIA_MEMMAP_MASK));
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}
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static uint8_t gfxnvidia_chip_readb(const struct flashctx *flash,
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const chipaddr addr)
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{
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return pci_mmio_readb(nvidia_bar + (addr & GFXNVIDIA_MEMMAP_MASK));
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}
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