mirror of
https://review.coreboot.org/flashrom.git
synced 2025-04-26 22:52:34 +02:00
75dc0655b9
Original progress reporting implemented in CB:49643 and it has some
issues, for example:
size_t start_address = start;
size_t end_address = len - start;
End address is anything but length minus start address.
update_progress(flash,
FLASHROM_PROGRESS_READ,
/*current*/ start - start_address + to_read,
/*total*/ end_address);
Total should just be length if that's how current value is computed.
---
libflashrom needs to know total size ahead of time.
That's init_progress() and changed update_progress().
It also needs to store the last current value to be able to update it.
That's stage_progress in flashrom_flashctx.
Measuring accurately amount of data which will be read/erased/written
isn't easy because things can be skipped as optimizations. The next
patch in the chain aims to address this, there are TODO/FIXME
comments there.
---
CLI shares terminal with the rest of the code and has to maintain more
state to handle that reasonably well.
Similar to CB:64668, an effort is made to keep the progress on a
single line. Non-progress output is kept track of to know when
moving to a new line cannot be avoided.
---
A script to test the CLI:
\#!/bin/bash
t=${1:-rewW}
shift
if [[ $t =~ r ]]; then
echo ">>> READ"
./flashrom -p dummy:emulate=W25Q128FV,freq=64mhz -r dump.rom --progress "$@"
echo
fi
if [[ $t =~ e ]]; then
echo ">>> ERASE"
./flashrom -p dummy:emulate=W25Q128FV,freq=64mhz -E --progress "$@"
echo
fi
if [[ $t =~ w ]]; then
echo ">>> WRITE (without erase)"
dd if=/dev/zero of=zero.rom bs=1M count=16 2> /dev/null
./flashrom -p dummy:emulate=W25Q128FV,freq=64mhz -w zero.rom --progress "$@"
echo
fi
if [[ $t =~ W ]]; then
echo ">>> WRITE (with erase)"
dd if=/dev/zero of=zero.rom bs=1M count=16 2> /dev/null
dd if=/dev/random of=random.rom bs=1M count=16 2> /dev/null
./flashrom -p dummy:emulate=W25Q128FV,freq=64mhz,image=random.rom -w zero.rom --progress "$@"
echo
fi
Co-developed-by: Anastasia Klimchuk <aklm@flashrom.org>
Co-developed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Change-Id: If1e40fc97f443c4f0c0501cef11cff1f3f84c051
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/84102
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
475 lines
14 KiB
C
475 lines
14 KiB
C
/*
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* This file is part of the flashrom project.
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*
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* Copyright (C) 2000 Silicon Integrated System Corporation
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* Copyright (C) 2006 Giampiero Giancipoli <gianci@email.it>
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* Copyright (C) 2006 coresystems GmbH <info@coresystems.de>
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* Copyright (C) 2007-2012 Carl-Daniel Hailfinger
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* Copyright (C) 2009 Sean Nelson <audiohacked@gmail.com>
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* Copyright (C) 2014 Stefan Tauner
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include "flash.h"
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#include "chipdrivers.h"
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#define MAX_REFLASH_TRIES 0x10
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#define MASK_FULL 0xffff
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#define MASK_2AA 0x7ff
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#define MASK_AAA 0xfff
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/* Check one byte for odd parity */
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uint8_t oddparity(uint8_t val)
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{
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val = (val ^ (val >> 4)) & 0xf;
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val = (val ^ (val >> 2)) & 0x3;
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return (val ^ (val >> 1)) & 0x1;
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}
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static void toggle_ready_jedec_common(const struct flashctx *flash, chipaddr dst, unsigned int delay)
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{
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unsigned int i = 0;
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uint8_t tmp1 = chip_readb(flash, dst) & 0x40;
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while (i++ < 0xFFFFFFF) {
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programmer_delay(flash, delay);
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uint8_t tmp2 = chip_readb(flash, dst) & 0x40;
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if (tmp1 == tmp2) {
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break;
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}
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tmp1 = tmp2;
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}
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if (i > 0x100000)
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msg_cdbg("%s: excessive loops, i=0x%x\n", __func__, i);
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}
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void toggle_ready_jedec(const struct flashctx *flash, chipaddr dst)
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{
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toggle_ready_jedec_common(flash, dst, 0);
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}
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/* Some chips require a minimum delay between toggle bit reads.
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* The Winbond W39V040C wants 50 ms between reads on sector erase toggle,
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* but experiments show that 2 ms are already enough. Pick a safety factor
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* of 4 and use an 8 ms delay.
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* Given that erase is slow on all chips, it is recommended to use
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* toggle_ready_jedec_slow in erase functions.
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*/
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static void toggle_ready_jedec_slow(const struct flashctx *flash)
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{
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const chipaddr dst = flash->virtual_memory;
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toggle_ready_jedec_common(flash, dst, 8 * 1000);
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}
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void data_polling_jedec(const struct flashctx *flash, chipaddr dst,
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uint8_t data)
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{
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unsigned int i = 0;
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data &= 0x80;
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while (i++ < 0xFFFFFFF) {
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uint8_t tmp = chip_readb(flash, dst) & 0x80;
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if (tmp == data) {
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break;
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}
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}
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if (i > 0x100000)
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msg_cdbg("%s: excessive loops, i=0x%x\n", __func__, i);
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}
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static unsigned int getaddrmask(const struct flashchip *chip)
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{
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switch (chip->feature_bits & FEATURE_ADDR_MASK) {
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case FEATURE_ADDR_FULL:
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return MASK_FULL;
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break;
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case FEATURE_ADDR_2AA:
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return MASK_2AA;
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break;
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case FEATURE_ADDR_AAA:
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return MASK_AAA;
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break;
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default:
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msg_cerr("%s called with unknown mask\n", __func__);
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return 0;
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break;
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}
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}
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static void start_program_jedec_common(const struct flashctx *flash)
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{
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const chipaddr bios = flash->virtual_memory;
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const bool shifted = (flash->chip->feature_bits & FEATURE_ADDR_SHIFTED);
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const unsigned int mask = getaddrmask(flash->chip);
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chip_writeb(flash, 0xAA, bios + ((shifted ? 0x2AAA : 0x5555) & mask));
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chip_writeb(flash, 0x55, bios + ((shifted ? 0x5555 : 0x2AAA) & mask));
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chip_writeb(flash, 0xA0, bios + ((shifted ? 0x2AAA : 0x5555) & mask));
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}
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int probe_jedec_29gl(struct flashctx *flash)
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{
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const unsigned int mask = getaddrmask(flash->chip);
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const chipaddr bios = flash->virtual_memory;
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const struct flashchip *chip = flash->chip;
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/* Reset chip to a clean slate */
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chip_writeb(flash, 0xF0, bios + (0x5555 & mask));
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/* Issue JEDEC Product ID Entry command */
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chip_writeb(flash, 0xAA, bios + (0x5555 & mask));
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chip_writeb(flash, 0x55, bios + (0x2AAA & mask));
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chip_writeb(flash, 0x90, bios + (0x5555 & mask));
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/* Read product ID */
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// FIXME: Continuation loop, second byte is at word 0x100/byte 0x200
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uint32_t man_id = chip_readb(flash, bios + 0x00);
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uint32_t dev_id = (chip_readb(flash, bios + 0x01) << 16) |
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(chip_readb(flash, bios + 0x0E) << 8) |
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(chip_readb(flash, bios + 0x0F) << 0);
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/* Issue JEDEC Product ID Exit command */
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chip_writeb(flash, 0xF0, bios + (0x5555 & mask));
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msg_cdbg("%s: man_id 0x%02"PRIx32", dev_id 0x%06"PRIx32"", __func__, man_id, dev_id);
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if (!oddparity(man_id))
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msg_cdbg(", man_id parity violation");
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/* Read the product ID location again. We should now see normal flash contents. */
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uint32_t flashcontent1 = chip_readb(flash, bios + 0x00); // FIXME: Continuation loop
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uint32_t flashcontent2 = (chip_readb(flash, bios + 0x01) << 16) |
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(chip_readb(flash, bios + 0x0E) << 8) |
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(chip_readb(flash, bios + 0x0F) << 0);
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if (man_id == flashcontent1)
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msg_cdbg(", man_id seems to be normal flash content");
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if (dev_id == flashcontent2)
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msg_cdbg(", dev_id seems to be normal flash content");
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msg_cdbg("\n");
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if (man_id != chip->manufacture_id || dev_id != chip->model_id)
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return 0;
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return 1;
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}
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static int probe_timings(const struct flashchip *chip, unsigned int *tenter, unsigned int *texit)
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{
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if (chip->probe_timing > 0) {
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*tenter = *texit = chip->probe_timing;
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} else if (chip->probe_timing == TIMING_ZERO) { /* No delay. */
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*tenter = *texit = 0;
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} else if (chip->probe_timing == TIMING_FIXME) { /* == _IGNORED */
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msg_cdbg("Chip lacks correct probe timing information, using default 10ms/40us. ");
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*tenter = 10000;
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*texit = 40;
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} else {
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msg_cerr("Chip has negative value in probe_timing, failing without chip access\n");
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return -1;
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}
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return 0;
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}
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int probe_jedec(struct flashctx *flash)
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{
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const chipaddr bios = flash->virtual_memory;
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const struct flashchip *chip = flash->chip;
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const bool shifted = (flash->chip->feature_bits & FEATURE_ADDR_SHIFTED);
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const unsigned int mask = getaddrmask(flash->chip);
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uint8_t id1, id2;
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uint32_t largeid1, largeid2;
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uint32_t flashcontent1, flashcontent2;
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unsigned int probe_timing_enter, probe_timing_exit;
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if (probe_timings(chip, &probe_timing_enter, &probe_timing_exit) < 0)
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return 0;
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/* Earlier probes might have been too fast for the chip to enter ID
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* mode completely. Allow the chip to finish this before seeing a
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* reset command.
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*/
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programmer_delay(flash, probe_timing_enter);
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/* Reset chip to a clean slate */
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if ((chip->feature_bits & FEATURE_RESET_MASK) == FEATURE_LONG_RESET) {
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chip_writeb(flash, 0xAA, bios + ((shifted ? 0x2AAA : 0x5555) & mask));
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if (probe_timing_exit)
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programmer_delay(flash, 10);
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chip_writeb(flash, 0x55, bios + ((shifted ? 0x5555 : 0x2AAA) & mask));
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if (probe_timing_exit)
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programmer_delay(flash, 10);
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}
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chip_writeb(flash, 0xF0, bios + ((shifted ? 0x2AAA : 0x5555) & mask));
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programmer_delay(flash, probe_timing_exit);
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/* Issue JEDEC Product ID Entry command */
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chip_writeb(flash, 0xAA, bios + ((shifted ? 0x2AAA : 0x5555) & mask));
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if (probe_timing_enter)
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programmer_delay(flash, 10);
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chip_writeb(flash, 0x55, bios + ((shifted ? 0x5555 : 0x2AAA) & mask));
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if (probe_timing_enter)
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programmer_delay(flash, 10);
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chip_writeb(flash, 0x90, bios + ((shifted ? 0x2AAA : 0x5555) & mask));
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programmer_delay(flash, probe_timing_enter);
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/* Read product ID */
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id1 = chip_readb(flash, bios + (0x00 << shifted));
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id2 = chip_readb(flash, bios + (0x01 << shifted));
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largeid1 = id1;
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largeid2 = id2;
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/* Check if it is a continuation ID, this should be a while loop. */
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if (id1 == 0x7F) {
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largeid1 <<= 8;
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id1 = chip_readb(flash, bios + 0x100);
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largeid1 |= id1;
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}
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if (id2 == 0x7F) {
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largeid2 <<= 8;
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id2 = chip_readb(flash, bios + 0x101);
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largeid2 |= id2;
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}
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/* Issue JEDEC Product ID Exit command */
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if ((chip->feature_bits & FEATURE_RESET_MASK) == FEATURE_LONG_RESET) {
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chip_writeb(flash, 0xAA, bios + ((shifted ? 0x2AAA : 0x5555) & mask));
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if (probe_timing_exit)
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programmer_delay(flash, 10);
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chip_writeb(flash, 0x55, bios + ((shifted ? 0x5555 : 0x2AAA) & mask));
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if (probe_timing_exit)
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programmer_delay(flash, 10);
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}
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chip_writeb(flash, 0xF0, bios + ((shifted ? 0x2AAA : 0x5555) & mask));
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programmer_delay(flash, probe_timing_exit);
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msg_cdbg("%s: id1 0x%02"PRIx32", id2 0x%02"PRIx32"", __func__, largeid1, largeid2);
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if (!oddparity(id1))
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msg_cdbg(", id1 parity violation");
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/* Read the product ID location again. We should now see normal flash contents. */
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flashcontent1 = chip_readb(flash, bios + (0x00 << shifted));
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flashcontent2 = chip_readb(flash, bios + (0x01 << shifted));
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/* Check if it is a continuation ID, this should be a while loop. */
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if (flashcontent1 == 0x7F) {
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flashcontent1 <<= 8;
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flashcontent1 |= chip_readb(flash, bios + 0x100);
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}
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if (flashcontent2 == 0x7F) {
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flashcontent2 <<= 8;
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flashcontent2 |= chip_readb(flash, bios + 0x101);
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}
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if (largeid1 == flashcontent1)
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msg_cdbg(", id1 is normal flash content");
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if (largeid2 == flashcontent2)
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msg_cdbg(", id2 is normal flash content");
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msg_cdbg("\n");
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if (largeid1 != chip->manufacture_id || largeid2 != chip->model_id)
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return 0;
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return 1;
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}
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static void issuecmd(const struct flashctx *flash, uint8_t op, unsigned int operand)
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{
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const chipaddr bios = flash->virtual_memory;
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bool shifted = (flash->chip->feature_bits & FEATURE_ADDR_SHIFTED);
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const unsigned int mask = getaddrmask(flash->chip);
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unsigned int delay_us = (flash->chip->probe_timing == TIMING_ZERO) ? 0 : 10;
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if (!operand)
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operand = (shifted ? 0x2AAA : 0x5555) & mask;
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chip_writeb(flash, 0xAA, bios + ((shifted ? 0x2AAA : 0x5555) & mask));
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programmer_delay(flash, delay_us);
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chip_writeb(flash, 0x55, bios + ((shifted ? 0x5555 : 0x2AAA) & mask));
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programmer_delay(flash, delay_us);
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chip_writeb(flash, op, bios + operand);
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programmer_delay(flash, delay_us);
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}
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int erase_sector_jedec(struct flashctx *flash, unsigned int page, unsigned int size)
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{
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/* Issue the Sector Erase command */
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issuecmd(flash, 0x80, 0);
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issuecmd(flash, 0x30, page);
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/* Wait for Toggle bit ready */
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toggle_ready_jedec_slow(flash);
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/* FIXME: Check the status register for errors. */
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return 0;
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}
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int erase_block_jedec(struct flashctx *flash, unsigned int block, unsigned int size)
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{
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/* Issue the Block Erase command */
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issuecmd(flash, 0x80, 0);
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issuecmd(flash, 0x50, block);
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/* Wait for Toggle bit ready */
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toggle_ready_jedec_slow(flash);
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/* FIXME: Check the status register for errors. */
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return 0;
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}
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/* erase chip with block_erase() prototype */
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int erase_chip_block_jedec(struct flashctx *flash, unsigned int addr, unsigned int blocksize)
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{
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if ((addr != 0) || (blocksize != flash->chip->total_size * 1024)) {
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msg_cerr("%s called with incorrect arguments\n", __func__);
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return -1;
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}
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/* Issue the JEDEC Chip Erase command */
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issuecmd(flash, 0x80, 0);
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issuecmd(flash, 0x10, 0);
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toggle_ready_jedec_slow(flash);
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/* FIXME: Check the status register for errors. */
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return 0;
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}
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static int write_byte_program_jedec_common(const struct flashctx *flash, const uint8_t *src,
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chipaddr dst)
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{
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int tries = 0;
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/* If the data is 0xFF, don't program it and don't complain. */
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if (*src == 0xFF) {
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return 0;
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}
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for (; tries < MAX_REFLASH_TRIES; tries++) {
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const chipaddr bios = flash->virtual_memory;
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/* Issue JEDEC Byte Program command */
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start_program_jedec_common(flash);
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/* transfer data from source to destination */
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chip_writeb(flash, *src, dst);
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toggle_ready_jedec(flash, bios);
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if (chip_readb(flash, dst) == *src)
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break;
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}
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return (tries >= MAX_REFLASH_TRIES) ? 1 : 0;
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}
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/* chunksize is 1 */
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int write_jedec_1(struct flashctx *flash, const uint8_t *src, unsigned int start,
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unsigned int len)
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{
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int failed = 0;
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chipaddr dst = flash->virtual_memory + start;
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const chipaddr olddst = dst;
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for (unsigned int i = 0; i < len; i++) {
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if (write_byte_program_jedec_common(flash, src, dst))
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failed = 1;
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dst++, src++;
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update_progress(flash, FLASHROM_PROGRESS_WRITE, 1);
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}
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if (failed)
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msg_cerr(" writing sector at 0x%" PRIxPTR " failed!\n", olddst);
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return failed;
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}
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static int jedec_write_page(struct flashctx *flash, const uint8_t *src,
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unsigned int start, unsigned int page_size)
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{
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int tries = 0, failed;
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const uint8_t *s = src;
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const chipaddr bios = flash->virtual_memory;
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chipaddr dst = bios + start;
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chipaddr d = dst;
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for (; tries < MAX_REFLASH_TRIES; tries++) {
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/* Issue JEDEC Start Program command */
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start_program_jedec_common(flash);
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/* transfer data from source to destination */
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for (unsigned int i = 0; i < page_size; i++) {
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/* If the data is 0xFF, don't program it */
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if (*src != 0xFF)
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chip_writeb(flash, *src, dst);
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dst++;
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src++;
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}
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toggle_ready_jedec(flash, dst - 1);
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dst = d;
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src = s;
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failed = verify_range(flash, src, start, page_size);
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if (!failed)
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|
break;
|
|
|
|
msg_cerr("retrying.\n");
|
|
}
|
|
|
|
if (failed) {
|
|
msg_cerr(" page 0x%" PRIxPTR " failed!\n", (d - bios) / page_size);
|
|
}
|
|
|
|
return failed;
|
|
}
|
|
|
|
/* chunksize is page_size */
|
|
/*
|
|
* Write a part of the flash chip.
|
|
* FIXME: Use the chunk code from Michael Karcher instead.
|
|
* This function is a slightly modified copy of spi_write_chunked.
|
|
* Each page is written separately in chunks with a maximum size of chunksize.
|
|
*/
|
|
int write_jedec(struct flashctx *flash, const uint8_t *buf, unsigned int start,
|
|
int unsigned len)
|
|
{
|
|
unsigned int starthere, lenhere;
|
|
/* FIXME: page_size is the wrong variable. We need max_writechunk_size
|
|
* in struct flashctx to do this properly. All chips using
|
|
* write_jedec have page_size set to max_writechunk_size, so
|
|
* we're OK for now.
|
|
*/
|
|
const unsigned int page_size = flash->chip->page_size;
|
|
const unsigned int nwrites = (start + len - 1) / page_size;
|
|
|
|
/* Warning: This loop has a very unusual condition and body.
|
|
* The loop needs to go through each page with at least one affected
|
|
* byte. The lowest page number is (start / page_size) since that
|
|
* division rounds down. The highest page number we want is the page
|
|
* where the last byte of the range lives. That last byte has the
|
|
* address (start + len - 1), thus the highest page number is
|
|
* (start + len - 1) / page_size. Since we want to include that last
|
|
* page as well, the loop condition uses <=.
|
|
*/
|
|
for (unsigned int i = start / page_size; i <= nwrites; i++) {
|
|
/* Byte position of the first byte in the range in this page. */
|
|
/* starthere is an offset to the base address of the chip. */
|
|
starthere = max(start, i * page_size);
|
|
/* Length of bytes in the range in this page. */
|
|
lenhere = min(start + len, (i + 1) * page_size) - starthere;
|
|
|
|
if (jedec_write_page(flash, buf + starthere - start, starthere, lenhere))
|
|
return 1;
|
|
update_progress(flash, FLASHROM_PROGRESS_WRITE, lenhere);
|
|
}
|
|
|
|
return 0;
|
|
}
|