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https://github.com/google/cpu_features.git
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627959faee
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8ca7c65f65
@ -82,6 +82,7 @@ typedef struct {
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int avx512_4fmaps : 1;
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int avx512_bf16 : 1;
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int avx512_vp2intersect : 1;
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int avx512_fp16 : 1;
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int amx_bf16 : 1;
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int amx_tile : 1;
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int amx_int8 : 1;
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@ -239,6 +240,7 @@ typedef enum {
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X86_AVX512_4FMAPS,
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X86_AVX512_BF16,
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X86_AVX512_VP2INTERSECT,
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X86_AVX512_FP16,
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X86_AMX_BF16,
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X86_AMX_TILE,
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X86_AMX_INT8,
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@ -365,6 +365,7 @@ static void ParseCpuId(const Leaves* leaves, X86Info* info,
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features->avx512_4fmaps = IsBitSet(leaf_7.edx, 3);
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features->avx512_bf16 = IsBitSet(leaf_7_1.eax, 5);
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features->avx512_vp2intersect = IsBitSet(leaf_7.edx, 8);
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features->avx512_fp16 = IsBitSet(leaf_7.edx, 23);
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}
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if (os_preserves->amx_registers) {
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features->amx_bf16 = IsBitSet(leaf_7.edx, 22);
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@ -1879,6 +1880,7 @@ CacheInfo GetX86CacheInfo(void) {
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LINE(X86_AVX512_4FMAPS, avx512_4fmaps, , , ) \
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LINE(X86_AVX512_BF16, avx512_bf16, , , ) \
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LINE(X86_AVX512_VP2INTERSECT, avx512_vp2intersect, , , ) \
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LINE(X86_AVX512_FP16, avx512_fp16, , , ) \
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LINE(X86_AMX_BF16, amx_bf16, , , ) \
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LINE(X86_AMX_TILE, amx_tile, , , ) \
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LINE(X86_AMX_INT8, amx_int8, , , ) \
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@ -944,6 +944,73 @@ TEST_F(CpuidX86Test, INTEL_ALDER_LAKE_AVX_VNNI) {
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EXPECT_EQ(GetX86Microarchitecture(&info), X86Microarchitecture::INTEL_ADL);
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}
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// https://github.com/InstLatx64/InstLatx64/blob/master/GenuineIntel/GenuineIntel0090672_AlderLake_BC_AVX512_CPUID01.txt
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TEST_F(CpuidX86Test, INTEL_ALDER_LAKE_AVX512) {
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cpu().SetOsBackupsExtendedRegisters(true);
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#if defined(CPU_FEATURES_OS_MACOS)
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cpu().SetDarwinSysCtlByName("hw.optional.avx512f");
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#endif
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cpu().SetLeaves({
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{{0x00000000, 0}, Leaf{0x00000020, 0x756E6547, 0x6C65746E, 0x49656E69}},
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{{0x00000001, 0}, Leaf{0x000906A4, 0x00400800, 0x7FFAFBBF, 0xBFEBFBFF}},
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{{0x00000007, 0}, Leaf{0x00000001, 0xF3BFA7EB, 0x98C07FEE, 0xFC9CC510}},
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{{0x00000007, 1}, Leaf{0x00401C30, 0x00000000, 0x00000000, 0x00000000}},
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});
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const auto info = GetX86Info();
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EXPECT_STREQ(info.vendor, CPU_FEATURES_VENDOR_GENUINE_INTEL);
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EXPECT_EQ(info.family, 0x06);
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EXPECT_EQ(info.model, 0x9A);
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EXPECT_TRUE(info.features.avx512f);
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EXPECT_TRUE(info.features.avx512bw);
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EXPECT_TRUE(info.features.avx512dq);
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EXPECT_TRUE(info.features.avx512cd);
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EXPECT_TRUE(info.features.avx512vl);
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EXPECT_TRUE(info.features.avx512_vp2intersect);
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EXPECT_TRUE(info.features.avx512vbmi);
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EXPECT_TRUE(info.features.avx512vbmi2);
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EXPECT_TRUE(info.features.avx512bitalg);
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EXPECT_TRUE(info.features.avx512vpopcntdq);
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EXPECT_TRUE(info.features.avx512ifma);
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EXPECT_TRUE(info.features.avx512_bf16);
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EXPECT_TRUE(info.features.avx512_fp16);
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EXPECT_EQ(GetX86Microarchitecture(&info), X86Microarchitecture::INTEL_ADL);
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}
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// https://github.com/InstLatx64/InstLatx64/blob/master/GenuineIntel/GenuineIntel00806C1_TigerLake_CPUID3.txt
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TEST_F(CpuidX86Test, INTEL_TIGER_LAKE_AVX512) {
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cpu().SetOsBackupsExtendedRegisters(true);
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#if defined(CPU_FEATURES_OS_MACOS)
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cpu().SetDarwinSysCtlByName("hw.optional.avx512f");
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#endif
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cpu().SetLeaves({
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{{0x00000000, 0}, Leaf{0x0000001B, 0x756E6547, 0x6C65746E, 0x49656E69}},
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{{0x00000001, 0}, Leaf{0x000806C1, 0x00100800, 0x7FFAFBBF, 0xBFEBFBFF}},
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{{0x00000007, 0}, Leaf{0x00000000, 0xF3BFA7EB, 0x18C05FCE, 0xFC100510}},
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});
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const auto info = GetX86Info();
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EXPECT_STREQ(info.vendor, CPU_FEATURES_VENDOR_GENUINE_INTEL);
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EXPECT_EQ(info.family, 0x06);
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EXPECT_EQ(info.model, 0x8C);
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EXPECT_TRUE(info.features.avx512f);
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EXPECT_TRUE(info.features.avx512bw);
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EXPECT_TRUE(info.features.avx512dq);
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EXPECT_TRUE(info.features.avx512cd);
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EXPECT_TRUE(info.features.avx512vl);
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EXPECT_TRUE(info.features.avx512_vp2intersect);
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EXPECT_TRUE(info.features.avx512vbmi);
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EXPECT_TRUE(info.features.avx512vbmi2);
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EXPECT_TRUE(info.features.avx512bitalg);
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EXPECT_TRUE(info.features.avx512vpopcntdq);
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EXPECT_TRUE(info.features.avx512ifma);
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EXPECT_EQ(GetX86Microarchitecture(&info), X86Microarchitecture::INTEL_TGL);
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}
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// http://users.atw.hu/instlatx64/AuthenticAMD/AuthenticAMD0100FA0_K10_Thuban_CPUID.txt
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TEST_F(CpuidX86Test, AMD_THUBAN_CACHE_INFO) {
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cpu().SetLeaves({
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