mirror of
https://github.com/google/cpu_features.git
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Add Windows Arm64 support (#291)
* Add Windows Arm64 support To add Windows Arm64 support was added detection of features via Windows API function IsProcessorFeaturePresent. Added _M_ARM64 to detect CPU_FEATURES_AARCH64 macro on Windows. Added initial code for Windows Arm64 testing and provided test for Raspberry PI 4. We can't use "define_introspection_and_hwcaps.inl" as a common file for all operating systems due to msvc compiler error C2099: initializer is not a constant, so as a workaround for Windows I used separate "define_introspection.inl" See also: #268, #284, #186 * [CMake] Add windows_utils.h to PROCESSOR_IS_AARCH64 * Add detection of armv8.1 atomic instructions * Update note on win-arm64 implementation and move to cpuinfo_aarch64.h * Remove redundant #ifdef CPU_FEATURES_OS_WINDOWS * Add note on FP/SIMD and Cryptographic Extension for win-arm64 * Add comments to Aarch64Info fields Added comments to specify that implementer, part and variant we set 0 for Windows, since Win API does not provide a way to get information. For revision added comment that we use GetNativeSystemInfo
This commit is contained in:
Mykola Hohsadze
GitHub
parent
273af56a15
commit
a6bf4f9031
@ -79,6 +79,7 @@ macro(add_cpu_features_headers_and_sources HDRS_LIST_NAME SRCS_LIST_NAME)
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list(APPEND ${HDRS_LIST_NAME} ${PROJECT_SOURCE_DIR}/include/cpuinfo_arm.h)
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elseif(PROCESSOR_IS_AARCH64)
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list(APPEND ${HDRS_LIST_NAME} ${PROJECT_SOURCE_DIR}/include/cpuinfo_aarch64.h)
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list(APPEND ${SRCS_LIST_NAME} ${PROJECT_SOURCE_DIR}/include/internal/windows_utils.h)
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elseif(PROCESSOR_IS_X86)
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list(APPEND ${HDRS_LIST_NAME} ${PROJECT_SOURCE_DIR}/include/cpuinfo_x86.h)
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list(APPEND ${SRCS_LIST_NAME} ${PROJECT_SOURCE_DIR}/include/internal/cpuid_x86.h)
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@ -39,7 +39,7 @@
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#define CPU_FEATURES_ARCH_ARM
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#endif
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#if defined(__aarch64__)
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#if (defined(__aarch64__) || defined(_M_ARM64))
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#define CPU_FEATURES_ARCH_AARCH64
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#endif
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@ -12,6 +12,100 @@
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// See the License for the specific language governing permissions and
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// limitations under the License.
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////////////////////////////////////////////////////////////////////////////////
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// A note on Windows AArch64 implementation
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////////////////////////////////////////////////////////////////////////////////
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// Getting cpu info via EL1 system registers is not possible, so we delegate it
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// to the Windows API (i.e., IsProcessorFeaturePresent and GetNativeSystemInfo).
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// The `implementer`, `variant` and `part` fields of the `Aarch64Info` struct
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// are not used, so they are set to 0. To get `revision` we use
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// `wProcessorRevision` from `SYSTEM_INFO`.
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//
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// Cryptographic Extension:
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// -----------------------------------------------------------------------------
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// According to documentation Arm Architecture Reference Manual for
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// A-profile architecture. A2.3 The Armv8 Cryptographic Extension. The Armv8.0
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// Cryptographic Extension provides instructions for the acceleration of
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// encryption and decryption, and includes the following features: FEAT_AES,
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// FEAT_PMULL, FEAT_SHA1, FEAT_SHA256.
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// see: https://developer.arm.com/documentation/ddi0487/latest
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//
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// We use `PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE` to detect all Armv8.0 crypto
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// features. This value reports all features or nothing, so even if you only
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// have support FEAT_AES and FEAT_PMULL, it will still return false.
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//
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// From Armv8.2, an implementation of the Armv8.0 Cryptographic Extension can
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// include either or both of:
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//
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// • The AES functionality, including support for multiplication of 64-bit
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// polynomials. The ID_AA64ISAR0_EL1.AES field indicates whether this
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// functionality is supported.
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// • The SHA1 and SHA2-256 functionality. The ID_AA64ISAR0_EL1.{SHA2, SHA1}
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// fields indicate whether this functionality is supported.
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//
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// ID_AA64ISAR0_EL1.AES, bits [7:4]:
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// Indicates support for AES instructions in AArch64 state. Defined values are:
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// - 0b0000 No AES instructions implemented.
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// - 0b0001 AESE, AESD, AESMC, and AESIMC instructions implemented.
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// - 0b0010 As for 0b0001, plus PMULL/PMULL2 instructions operating on 64-bit
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// data quantities.
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//
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// FEAT_AES implements the functionality identified by the value 0b0001.
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// FEAT_PMULL implements the functionality identified by the value 0b0010.
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// From Armv8, the permitted values are 0b0000 and 0b0010.
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//
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// ID_AA64ISAR0_EL1.SHA1, bits [11:8]:
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// Indicates support for SHA1 instructions in AArch64 state. Defined values are:
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// - 0b0000 No SHA1 instructions implemented.
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// - 0b0001 SHA1C, SHA1P, SHA1M, SHA1H, SHA1SU0, and SHA1SU1 instructions
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// implemented.
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//
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// FEAT_SHA1 implements the functionality identified by the value 0b0001.
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// From Armv8, the permitted values are 0b0000 and 0b0001.
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// If the value of ID_AA64ISAR0_EL1.SHA2 is 0b0000, this field must have the
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// value 0b0000.
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//
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// ID_AA64ISAR0_EL1.SHA2, bits [15:12]:
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// Indicates support for SHA2 instructions in AArch64 state. Defined values are:
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// - 0b0000 No SHA2 instructions implemented.
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// - 0b0001 Implements instructions: SHA256H, SHA256H2, SHA256SU0, and
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// SHA256SU1.
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// - 0b0010 Implements instructions:
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// • SHA256H, SHA256H2, SHA256SU0, and SHA256SU1.
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// • SHA512H, SHA512H2, SHA512SU0, and SHA512SU1.
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//
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// FEAT_SHA256 implements the functionality identified by the value 0b0001.
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// FEAT_SHA512 implements the functionality identified by the value 0b0010.
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//
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// In Armv8, the permitted values are 0b0000 and 0b0001.
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// From Armv8.2, the permitted values are 0b0000, 0b0001, and 0b0010.
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//
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// If the value of ID_AA64ISAR0_EL1.SHA1 is 0b0000, this field must have the
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// value 0b0000.
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//
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// If the value of this field is 0b0010, ID_AA64ISAR0_EL1.SHA3
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// must have the value 0b0001.
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//
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// Other cryptographic features that we cannot detect such as sha512, sha3, sm3,
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// sm4, sveaes, svepmull, svesha3, svesm4 we set to 0.
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//
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// FP/SIMD:
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// -----------------------------------------------------------------------------
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// FP/SIMD must be implemented on all Armv8.0 implementations, but
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// implementations targeting specialized markets may support the following
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// combinations:
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//
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// • No NEON or floating-point.
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// • Full floating-point and SIMD support with exception trapping.
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// • Full floating-point and SIMD support without exception trapping.
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//
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// ref:
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// https://developer.arm.com/documentation/den0024/a/AArch64-Floating-point-and-NEON
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//
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// So, we use `PF_ARM_VFP_32_REGISTERS_AVAILABLE`,
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// `PF_ARM_NEON_INSTRUCTIONS_AVAILABLE` to detect `asimd` and `fp`
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#ifndef CPU_FEATURES_INCLUDE_CPUINFO_AARCH64_H_
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#define CPU_FEATURES_INCLUDE_CPUINFO_AARCH64_H_
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@ -81,10 +175,11 @@ typedef struct {
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typedef struct {
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Aarch64Features features;
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int implementer;
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int variant;
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int part;
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int revision;
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int implementer; // We set 0 for Windows.
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int variant; // We set 0 for Windows.
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int part; // We set 0 for Windows.
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int revision; // We use GetNativeSystemInfo to get processor revision for
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// Windows.
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} Aarch64Info;
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Aarch64Info GetAarch64Info(void);
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@ -34,5 +34,37 @@
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#define PF_SSE4_2_INSTRUCTIONS_AVAILABLE 38
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#endif
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#if !defined(PF_ARM_VFP_32_REGISTERS_AVAILABLE)
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#define PF_ARM_VFP_32_REGISTERS_AVAILABLE 18
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#endif
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#if !defined(PF_ARM_NEON_INSTRUCTIONS_AVAILABLE)
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#define PF_ARM_NEON_INSTRUCTIONS_AVAILABLE 19
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#endif
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#if !defined(PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE)
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#define PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE 30
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#endif
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#if !defined(PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE)
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#define PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE 31
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#endif
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#if !defined(PF_ARM_V81_ATOMIC_INSTRUCTIONS_AVAILABLE)
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#define PF_ARM_V81_ATOMIC_INSTRUCTIONS_AVAILABLE 34
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#endif
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#if !defined(PF_ARM_V82_DP_INSTRUCTIONS_AVAILABLE)
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#define PF_ARM_V82_DP_INSTRUCTIONS_AVAILABLE 43
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#endif
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#if !defined(PF_ARM_V83_JSCVT_INSTRUCTIONS_AVAILABLE)
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#define PF_ARM_V83_JSCVT_INSTRUCTIONS_AVAILABLE 44
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#endif
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#if !defined(PF_ARM_V83_LRCPC_INSTRUCTIONS_AVAILABLE)
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#define PF_ARM_V83_LRCPC_INSTRUCTIONS_AVAILABLE 45
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#endif
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#endif // CPU_FEATURES_OS_WINDOWS
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#endif // CPU_FEATURES_INCLUDE_INTERNAL_WINDOWS_UTILS_H_
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138
src/impl_aarch64_windows.c
Normal file
138
src/impl_aarch64_windows.c
Normal file
@ -0,0 +1,138 @@
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// Copyright 2023 Google LLC
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "cpu_features_macros.h"
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#ifdef CPU_FEATURES_ARCH_AARCH64
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#ifdef CPU_FEATURES_OS_WINDOWS
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#include "cpuinfo_aarch64.h"
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////////////////////////////////////////////////////////////////////////////////
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// Definitions for introspection.
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////////////////////////////////////////////////////////////////////////////////
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#define INTROSPECTION_TABLE \
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LINE(AARCH64_FP, fp, , , ) \
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LINE(AARCH64_ASIMD, asimd, , , ) \
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LINE(AARCH64_EVTSTRM, evtstrm, , , ) \
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LINE(AARCH64_AES, aes, , , ) \
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LINE(AARCH64_PMULL, pmull, , , ) \
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LINE(AARCH64_SHA1, sha1, , , ) \
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LINE(AARCH64_SHA2, sha2, , , ) \
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LINE(AARCH64_CRC32, crc32, , , ) \
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LINE(AARCH64_ATOMICS, atomics, , , ) \
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LINE(AARCH64_FPHP, fphp, , , ) \
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LINE(AARCH64_ASIMDHP, asimdhp, , , ) \
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LINE(AARCH64_CPUID, cpuid, , , ) \
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LINE(AARCH64_ASIMDRDM, asimdrdm, , , ) \
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LINE(AARCH64_JSCVT, jscvt, , , ) \
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LINE(AARCH64_FCMA, fcma, , , ) \
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LINE(AARCH64_LRCPC, lrcpc, , , ) \
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LINE(AARCH64_DCPOP, dcpop, , , ) \
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LINE(AARCH64_SHA3, sha3, , , ) \
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LINE(AARCH64_SM3, sm3, , , ) \
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LINE(AARCH64_SM4, sm4, , , ) \
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LINE(AARCH64_ASIMDDP, asimddp, , , ) \
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LINE(AARCH64_SHA512, sha512, , , ) \
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LINE(AARCH64_SVE, sve, , , ) \
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LINE(AARCH64_ASIMDFHM, asimdfhm, , , ) \
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LINE(AARCH64_DIT, dit, , , ) \
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LINE(AARCH64_USCAT, uscat, , , ) \
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LINE(AARCH64_ILRCPC, ilrcpc, , , ) \
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LINE(AARCH64_FLAGM, flagm, , , ) \
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LINE(AARCH64_SSBS, ssbs, , , ) \
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LINE(AARCH64_SB, sb, , , ) \
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LINE(AARCH64_PACA, paca, , , ) \
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LINE(AARCH64_PACG, pacg, , , ) \
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LINE(AARCH64_DCPODP, dcpodp, , , ) \
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LINE(AARCH64_SVE2, sve2, , , ) \
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LINE(AARCH64_SVEAES, sveaes, , , ) \
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LINE(AARCH64_SVEPMULL, svepmull, , , ) \
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LINE(AARCH64_SVEBITPERM, svebitperm, , , ) \
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LINE(AARCH64_SVESHA3, svesha3, , , ) \
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LINE(AARCH64_SVESM4, svesm4, , , ) \
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LINE(AARCH64_FLAGM2, flagm2, , , ) \
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LINE(AARCH64_FRINT, frint, , , ) \
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LINE(AARCH64_SVEI8MM, svei8mm, , , ) \
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LINE(AARCH64_SVEF32MM, svef32mm, , , ) \
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LINE(AARCH64_SVEF64MM, svef64mm, , , ) \
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LINE(AARCH64_SVEBF16, svebf16, , , ) \
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LINE(AARCH64_I8MM, i8mm, , , ) \
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LINE(AARCH64_BF16, bf16, , , ) \
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LINE(AARCH64_DGH, dgh, , , ) \
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LINE(AARCH64_RNG, rng, , , ) \
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LINE(AARCH64_BTI, bti, , , ) \
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LINE(AARCH64_MTE, mte, , , ) \
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LINE(AARCH64_ECV, ecv, , , ) \
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LINE(AARCH64_AFP, afp, , , ) \
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LINE(AARCH64_RPRES, rpres, , , )
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#define INTROSPECTION_PREFIX Aarch64
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#define INTROSPECTION_ENUM_PREFIX AARCH64
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#include "define_introspection.inl"
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////////////////////////////////////////////////////////////////////////////////
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// Implementation.
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////////////////////////////////////////////////////////////////////////////////
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#include <stdbool.h>
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#include "internal/windows_utils.h"
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#ifdef CPU_FEATURES_MOCK_CPUID_AARCH64
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extern bool GetWindowsIsProcessorFeaturePresent(DWORD);
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extern WORD GetWindowsNativeSystemInfoProcessorRevision();
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#else // CPU_FEATURES_MOCK_CPUID_AARCH64
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static bool GetWindowsIsProcessorFeaturePresent(DWORD dwProcessorFeature) {
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return IsProcessorFeaturePresent(dwProcessorFeature);
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}
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static WORD GetWindowsNativeSystemInfoProcessorRevision() {
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SYSTEM_INFO system_info;
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GetNativeSystemInfo(&system_info);
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return system_info.wProcessorRevision;
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}
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#endif
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static const Aarch64Info kEmptyAarch64Info;
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Aarch64Info GetAarch64Info(void) {
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Aarch64Info info = kEmptyAarch64Info;
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info.revision = GetWindowsNativeSystemInfoProcessorRevision();
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info.features.fp =
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GetWindowsIsProcessorFeaturePresent(PF_ARM_VFP_32_REGISTERS_AVAILABLE);
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info.features.asimd =
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GetWindowsIsProcessorFeaturePresent(PF_ARM_NEON_INSTRUCTIONS_AVAILABLE);
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info.features.crc32 = GetWindowsIsProcessorFeaturePresent(
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PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE);
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info.features.asimddp =
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GetWindowsIsProcessorFeaturePresent(PF_ARM_V82_DP_INSTRUCTIONS_AVAILABLE);
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info.features.jscvt = GetWindowsIsProcessorFeaturePresent(
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PF_ARM_V83_JSCVT_INSTRUCTIONS_AVAILABLE);
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info.features.lrcpc = GetWindowsIsProcessorFeaturePresent(
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PF_ARM_V83_LRCPC_INSTRUCTIONS_AVAILABLE);
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info.features.atomics = GetWindowsIsProcessorFeaturePresent(
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PF_ARM_V81_ATOMIC_INSTRUCTIONS_AVAILABLE);
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bool is_crypto_available = GetWindowsIsProcessorFeaturePresent(
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PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE);
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info.features.aes = is_crypto_available;
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info.features.sha1 = is_crypto_available;
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info.features.sha2 = is_crypto_available;
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info.features.pmull = is_crypto_available;
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return info;
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}
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#endif // CPU_FEATURES_OS_WINDOWS
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#endif // CPU_FEATURES_ARCH_AARCH64
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@ -71,7 +71,11 @@ endif()
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##------------------------------------------------------------------------------
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## cpuinfo_aarch64_test
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if(PROCESSOR_IS_AARCH64)
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add_executable(cpuinfo_aarch64_test cpuinfo_aarch64_test.cc ../src/impl_aarch64_linux_or_android.c)
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add_executable(cpuinfo_aarch64_test
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cpuinfo_aarch64_test.cc
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../src/impl_aarch64_linux_or_android.c
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../src/impl_aarch64_windows.c)
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target_compile_definitions(cpuinfo_aarch64_test PUBLIC CPU_FEATURES_MOCK_CPUID_AARCH64)
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target_link_libraries(cpuinfo_aarch64_test all_libraries)
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add_test(NAME cpuinfo_aarch64_test COMMAND cpuinfo_aarch64_test)
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endif()
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@ -14,27 +14,88 @@
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#include "cpuinfo_aarch64.h"
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#include <set>
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#include "filesystem_for_testing.h"
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#include "gtest/gtest.h"
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#include "hwcaps_for_testing.h"
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#if defined(CPU_FEATURES_OS_WINDOWS)
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#include "internal/windows_utils.h"
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#endif // CPU_FEATURES_OS_WINDOWS
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namespace cpu_features {
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class FakeCpuAarch64 {
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public:
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#if defined(CPU_FEATURES_OS_WINDOWS)
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bool GetWindowsIsProcessorFeaturePresent(DWORD dwProcessorFeature) {
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return windows_isprocessorfeaturepresent_.count(dwProcessorFeature);
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}
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void SetWindowsIsProcessorFeaturePresent(DWORD dwProcessorFeature) {
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windows_isprocessorfeaturepresent_.insert(dwProcessorFeature);
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}
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WORD GetWindowsNativeSystemInfoProcessorRevision() const {
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return processor_revision_;
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}
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void SetWindowsNativeSystemInfoProcessorRevision(WORD wProcessorRevision) {
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processor_revision_ = wProcessorRevision;
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}
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private:
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std::set<DWORD> windows_isprocessorfeaturepresent_;
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WORD processor_revision_{};
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#endif // CPU_FEATURES_OS_WINDOWS
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};
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static FakeCpuAarch64* g_fake_cpu_instance = nullptr;
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static FakeCpuAarch64& cpu() {
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assert(g_fake_cpu_instance != nullptr);
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return *g_fake_cpu_instance;
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}
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#if defined(CPU_FEATURES_OS_WINDOWS)
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extern "C" bool GetWindowsIsProcessorFeaturePresent(DWORD dwProcessorFeature) {
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return cpu().GetWindowsIsProcessorFeaturePresent(dwProcessorFeature);
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}
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extern "C" WORD GetWindowsNativeSystemInfoProcessorRevision() {
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return cpu().GetWindowsNativeSystemInfoProcessorRevision();
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}
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#endif // CPU_FEATURES_OS_WINDOWS
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|
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namespace {
|
||||
|
||||
void DisableHardwareCapabilities() { SetHardwareCapabilities(0, 0); }
|
||||
class CpuidAarch64Test : public ::testing::Test {
|
||||
protected:
|
||||
void SetUp() override {
|
||||
assert(g_fake_cpu_instance == nullptr);
|
||||
g_fake_cpu_instance = new FakeCpuAarch64();
|
||||
}
|
||||
void TearDown() override {
|
||||
delete g_fake_cpu_instance;
|
||||
g_fake_cpu_instance = nullptr;
|
||||
}
|
||||
};
|
||||
|
||||
TEST(CpuinfoAarch64Test, Aarch64FeaturesEnum) {
|
||||
const char *last_name = GetAarch64FeaturesEnumName(AARCH64_LAST_);
|
||||
EXPECT_STREQ(last_name, "unknown_feature");
|
||||
for (int i = static_cast<int>(AARCH64_FP); i != static_cast<int>(AARCH64_LAST_); ++i) {
|
||||
const auto feature = static_cast<Aarch64FeaturesEnum>(i);
|
||||
const char *name = GetAarch64FeaturesEnumName(feature);
|
||||
ASSERT_FALSE(name == nullptr);
|
||||
EXPECT_STRNE(name, "");
|
||||
EXPECT_STRNE(name, last_name);
|
||||
}
|
||||
const char* last_name = GetAarch64FeaturesEnumName(AARCH64_LAST_);
|
||||
EXPECT_STREQ(last_name, "unknown_feature");
|
||||
for (int i = static_cast<int>(AARCH64_FP);
|
||||
i != static_cast<int>(AARCH64_LAST_); ++i) {
|
||||
const auto feature = static_cast<Aarch64FeaturesEnum>(i);
|
||||
const char* name = GetAarch64FeaturesEnumName(feature);
|
||||
ASSERT_FALSE(name == nullptr);
|
||||
EXPECT_STRNE(name, "");
|
||||
EXPECT_STRNE(name, last_name);
|
||||
}
|
||||
}
|
||||
|
||||
#if defined(CPU_FEATURES_OS_LINUX)
|
||||
void DisableHardwareCapabilities() { SetHardwareCapabilities(0, 0); }
|
||||
|
||||
TEST(CpuinfoAarch64Test, FromHardwareCap) {
|
||||
ResetHwcaps();
|
||||
SetHardwareCapabilities(AARCH64_HWCAP_FP | AARCH64_HWCAP_AES, 0);
|
||||
@ -184,6 +245,32 @@ CPU revision : 3)");
|
||||
EXPECT_FALSE(info.features.afp);
|
||||
EXPECT_FALSE(info.features.rpres);
|
||||
}
|
||||
#endif // CPU_FEATURES_OS_LINUX
|
||||
|
||||
#if defined(CPU_FEATURES_OS_WINDOWS)
|
||||
TEST_F(CpuidAarch64Test, WINDOWS_AARCH64_RPI4) {
|
||||
cpu().SetWindowsNativeSystemInfoProcessorRevision(0x03);
|
||||
cpu().SetWindowsIsProcessorFeaturePresent(PF_ARM_VFP_32_REGISTERS_AVAILABLE);
|
||||
cpu().SetWindowsIsProcessorFeaturePresent(PF_ARM_NEON_INSTRUCTIONS_AVAILABLE);
|
||||
cpu().SetWindowsIsProcessorFeaturePresent(
|
||||
PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE);
|
||||
|
||||
const auto info = GetAarch64Info();
|
||||
|
||||
EXPECT_EQ(info.revision, 0x03);
|
||||
EXPECT_TRUE(info.features.fp);
|
||||
EXPECT_TRUE(info.features.asimd);
|
||||
EXPECT_TRUE(info.features.crc32);
|
||||
EXPECT_FALSE(info.features.aes);
|
||||
EXPECT_FALSE(info.features.sha1);
|
||||
EXPECT_FALSE(info.features.sha2);
|
||||
EXPECT_FALSE(info.features.pmull);
|
||||
EXPECT_FALSE(info.features.atomics);
|
||||
EXPECT_FALSE(info.features.asimddp);
|
||||
EXPECT_FALSE(info.features.jscvt);
|
||||
EXPECT_FALSE(info.features.lrcpc);
|
||||
}
|
||||
#endif // CPU_FEATURES_OS_WINDOWS
|
||||
|
||||
} // namespace
|
||||
} // namespace cpu_features
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user