mirror of
https://github.com/google/cpu_features.git
synced 2025-04-27 23:22:31 +02:00
Support risc-v (#287)
Co-authored-by: DaniAffCH <danieleaffinita2000@gmail.com> Co-authored-by: Corentin Le Molgat <corentinl@google.com>
This commit is contained in:
Guillaume Chatelet
GitHub
parent
a7ea4a7783
commit
c919e9aa77
28
.github/workflows/riscv_linux_cmake.yml
vendored
Normal file
28
.github/workflows/riscv_linux_cmake.yml
vendored
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@ -0,0 +1,28 @@
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name: RISCV Linux CMake
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on:
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push:
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pull_request:
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schedule:
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# min hours day(month) month day(week)
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- cron: '0 0 7,22 * *'
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jobs:
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# Building using the github runner environement directly.
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make:
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runs-on: ubuntu-latest
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strategy:
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matrix:
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targets: [
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[riscv32],
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[riscv64],
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]
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fail-fast: false
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env:
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TARGET: ${{ matrix.targets[0] }}
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steps:
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- uses: actions/checkout@v2
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- name: Build
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run: make --directory=cmake/ci ${TARGET}_build
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- name: Test
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run: make --directory=cmake/ci ${TARGET}_test
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@ -50,6 +50,7 @@ set(PROCESSOR_IS_AARCH64 FALSE)
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set(PROCESSOR_IS_X86 FALSE)
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set(PROCESSOR_IS_POWER FALSE)
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set(PROCESSOR_IS_S390X FALSE)
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set(PROCESSOR_IS_RISCV FALSE)
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if(CMAKE_SYSTEM_PROCESSOR MATCHES "^mips")
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set(PROCESSOR_IS_MIPS TRUE)
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@ -63,6 +64,8 @@ elseif(CMAKE_SYSTEM_PROCESSOR MATCHES "^(powerpc|ppc)")
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set(PROCESSOR_IS_POWER TRUE)
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elseif(CMAKE_SYSTEM_PROCESSOR MATCHES "^(s390x)")
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set(PROCESSOR_IS_S390X TRUE)
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elseif(CMAKE_SYSTEM_PROCESSOR MATCHES "^riscv")
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set(PROCESSOR_IS_RISCV TRUE)
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endif()
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macro(add_cpu_features_headers_and_sources HDRS_LIST_NAME SRCS_LIST_NAME)
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@ -84,6 +87,8 @@ macro(add_cpu_features_headers_and_sources HDRS_LIST_NAME SRCS_LIST_NAME)
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list(APPEND ${HDRS_LIST_NAME} ${PROJECT_SOURCE_DIR}/include/cpuinfo_ppc.h)
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elseif(PROCESSOR_IS_S390X)
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list(APPEND ${HDRS_LIST_NAME} ${PROJECT_SOURCE_DIR}/include/cpuinfo_s390x.h)
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elseif(PROCESSOR_IS_RISCV)
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list(APPEND ${HDRS_LIST_NAME} ${PROJECT_SOURCE_DIR}/include/cpuinfo_riscv.h)
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else()
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message(FATAL_ERROR "Unsupported architectures ${CMAKE_SYSTEM_PROCESSOR}")
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endif()
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38
README.md
38
README.md
@ -7,12 +7,12 @@ instructions) at runtime.
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[comment]: <> (The following lines are generated by "scripts/generate_badges.d" that you can run online https://run.dlang.io/)
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| Os | amd64 | AArch64 | ARM | MIPS | s390x | POWER |
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| :-- | --: | --: | --: | --: | --: | --: |
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| Linux | [![][i1a0]][l1a0]<br/>[![][i1a1]][l1a1] | [![][i1b0]][l1b0]<br/>![][d1] | [![][i1c0]][l1c0]<br/>![][d1] | [![][i1d0]][l1d0]<br/>![][d1] | [![][i1e0]][l1e0]<br/>![][d1] | [![][i1f0]][l1f0]<br/>![][d1] |
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| FreeBSD | [![][i2a0]][l2a0]<br/>![][d1] | ![][d0]<br/>![][d1] | ![][d0]<br/>![][d1] | ![][d0]<br/>![][d1] | ![][d0]<br/>![][d1] | ![][d0]<br/>![][d1] |
|
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| MacOS | [![][i3a0]][l3a0]<br/>![][d1] | ![][d0]<br/>![][d1] | ![][d0]<br/>![][d1] | ![][d0]<br/>![][d1] | ![][d0]<br/>![][d1] | ![][d0]<br/>![][d1] |
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| Windows | [![][i4a0]][l4a0]<br/>![][d1] | ![][d0]<br/>![][d1] | ![][d0]<br/>![][d1] | ![][d0]<br/>![][d1] | ![][d0]<br/>![][d1] | ![][d0]<br/>![][d1] |
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| Os | amd64 | AArch64 | ARM | MIPS | POWER | RISCV | s390x |
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| :-- | --: | --: | --: | --: | --: | --: | --: |
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| Linux | [![][i1a0]][l1a0]<br/>[![][i1a1]][l1a1] | [![][i1b0]][l1b0]<br/>![][d1] | [![][i1c0]][l1c0]<br/>![][d1] | [![][i1d0]][l1d0]<br/>![][d1] | [![][i1e0]][l1e0]<br/>![][d1] | [![][i1f0]][l1f0]<br/>![][d1] | [![][i1g0]][l1g0]<br/>![][d1] |
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| FreeBSD | [![][i2a0]][l2a0]<br/>![][d1] | ![][d0]<br/>![][d1] | ![][d0]<br/>![][d1] | ![][d0]<br/>![][d1] | ![][d0]<br/>![][d1] | ![][d0]<br/>![][d1] | ![][d0]<br/>![][d1] |
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| MacOS | [![][i3a0]][l3a0]<br/>![][d1] | ![][d0]<br/>![][d1] | ![][d0]<br/>![][d1] | ![][d0]<br/>![][d1] | ![][d0]<br/>![][d1] | ![][d0]<br/>![][d1] | ![][d0]<br/>![][d1] |
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| Windows | [![][i4a0]][l4a0]<br/>![][d1] | ![][d0]<br/>![][d1] | ![][d0]<br/>![][d1] | ![][d0]<br/>![][d1] | ![][d0]<br/>![][d1] | ![][d0]<br/>![][d1] | ![][d0]<br/>![][d1] |
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[d0]: https://img.shields.io/badge/CMake-N%2FA-lightgrey
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[d1]: https://img.shields.io/badge/Bazel-N%2FA-lightgrey
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@ -21,8 +21,9 @@ instructions) at runtime.
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[i1b0]: https://img.shields.io/github/workflow/status/google/cpu_features/AArch64%20Linux%20CMake/main?label=CMake
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[i1c0]: https://img.shields.io/github/workflow/status/google/cpu_features/ARM%20Linux%20CMake/main?label=CMake
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[i1d0]: https://img.shields.io/github/workflow/status/google/cpu_features/MIPS%20Linux%20CMake/main?label=CMake
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[i1e0]: https://img.shields.io/github/workflow/status/google/cpu_features/s390x%20Linux%20CMake/main?label=CMake
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[i1f0]: https://img.shields.io/github/workflow/status/google/cpu_features/POWER%20Linux%20CMake/main?label=CMake
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[i1e0]: https://img.shields.io/github/workflow/status/google/cpu_features/POWER%20Linux%20CMake/main?label=CMake
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[i1f0]: https://img.shields.io/github/workflow/status/google/cpu_features/RISCV%20Linux%20CMake/main?label=CMake
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[i1g0]: https://img.shields.io/github/workflow/status/google/cpu_features/s390x%20Linux%20CMake/main?label=CMake
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[i2a0]: https://img.shields.io/github/workflow/status/google/cpu_features/amd64%20FreeBSD%20CMake/main?label=CMake
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[i3a0]: https://img.shields.io/github/workflow/status/google/cpu_features/amd64%20MacOS%20CMake/main?label=CMake
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[i4a0]: https://img.shields.io/github/workflow/status/google/cpu_features/amd64%20Windows%20CMake/main?label=CMake
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@ -31,8 +32,9 @@ instructions) at runtime.
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[l1b0]: https://github.com/google/cpu_features/actions/workflows/aarch64_linux_cmake.yml
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[l1c0]: https://github.com/google/cpu_features/actions/workflows/arm_linux_cmake.yml
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[l1d0]: https://github.com/google/cpu_features/actions/workflows/mips_linux_cmake.yml
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[l1e0]: https://github.com/google/cpu_features/actions/workflows/s390x_linux_cmake.yml
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[l1f0]: https://github.com/google/cpu_features/actions/workflows/power_linux_cmake.yml
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[l1e0]: https://github.com/google/cpu_features/actions/workflows/power_linux_cmake.yml
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[l1f0]: https://github.com/google/cpu_features/actions/workflows/riscv_linux_cmake.yml
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[l1g0]: https://github.com/google/cpu_features/actions/workflows/s390x_linux_cmake.yml
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[l2a0]: https://github.com/google/cpu_features/actions/workflows/amd64_freebsd_cmake.yml
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[l3a0]: https://github.com/google/cpu_features/actions/workflows/amd64_macos_cmake.yml
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[l4a0]: https://github.com/google/cpu_features/actions/workflows/amd64_windows_cmake.yml
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@ -176,14 +178,14 @@ flags : aes,avx,cx16,smx,sse4_1,sse4_2,ssse3
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<a name="support"></a>
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## What's supported
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| | x86³ | AArch64 | ARM | MIPS⁴ | s390x | POWER |
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|---------|:----:|:-------:|:-------:|:-------:|:-------:|:-------:|
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| Linux | yes² | yes¹ | yes¹ | yes¹ | yes¹ | yes¹ |
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| FreeBSD | yes² | not yet | not yet | not yet | not yet | not yet |
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| MacOs | yes² | not yet | N/A | N/A | no | no |
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| Windows | yes² | not yet | not yet | N/A | N/A | N/A |
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| Android | yes² | yes¹ | yes¹ | yes¹ | N/A | N/A |
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| iOS | N/A | not yet | not yet | N/A | N/A | N/A |
|
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| | x86³ | AArch64 | ARM | MIPS⁴ | POWER | RISCV | s390x |
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|---------|:----:|:-------:|:-------:|:-------:|:-------:|:-------:|:-------:|
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| Linux | yes² | yes¹ | yes¹ | yes¹ | yes¹ | yes¹ | yes¹ |
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||||
| FreeBSD | yes² | not yet | not yet | not yet | not yet | N/A | not yet |
|
||||
| MacOs | yes² | not yet | N/A | N/A | no | N/A | no |
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||||
| Windows | yes² | not yet | not yet | N/A | N/A | N/A | N/A |
|
||||
| Android | yes² | yes¹ | yes¹ | yes¹ | N/A | N/A | N/A |
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||||
| iOS | N/A | not yet | not yet | N/A | N/A | N/A | N/A |
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1. **Features revealed from Linux.** We gather data from several sources
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depending on availability:
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@ -55,6 +55,8 @@ help:
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@echo -e "\t\t${BOLD}ppc${RESET} (bootlin toolchain)"
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@echo -e "\t\t${BOLD}ppc64${RESET} (bootlin toolchain)"
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@echo -e "\t\t${BOLD}ppc64le${RESET} (bootlin toolchain)"
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@echo -e "\t\t${BOLD}riscv32${RESET} (bootlin toolchain)"
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@echo -e "\t\t${BOLD}riscv64${RESET} (bootlin toolchain)"
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@echo -e "\t\t${BOLD}s390x${RESET} (bootlin toolchain)"
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@echo
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@echo -e "\tWith ${BOLD}<toolchain_stage>${RESET}:"
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@ -154,6 +156,7 @@ TOOLCHAIN_TARGETS = \
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aarch64-linux-gnu aarch64_be-linux-gnu \
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mips32 mips32el mips64 mips64el \
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ppc ppc64 ppc64le \
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riscv32 riscv64 \
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s390x
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TOOLCHAIN_STAGES = env devel build test
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define toolchain-stage-target =
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70
include/cpuinfo_riscv.h
Normal file
70
include/cpuinfo_riscv.h
Normal file
@ -0,0 +1,70 @@
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// Copyright 2022 Google LLC
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
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// See the License for the specific language governing permissions and
|
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// limitations under the License.
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#ifndef CPU_FEATURES_INCLUDE_CPUINFO_RISCV_H_
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#define CPU_FEATURES_INCLUDE_CPUINFO_RISCV_H_
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#include "cpu_features_cache_info.h"
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#include "cpu_features_macros.h"
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#if !defined(CPU_FEATURES_ARCH_RISCV)
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#error "Including cpuinfo_riscv.h from a non-riscv target."
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#endif
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CPU_FEATURES_START_CPP_NAMESPACE
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typedef struct {
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// Base
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int RV32I : 1; // Base Integer Instruction Set, 32-bit
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int RV64I : 1; // Base Integer Instruction Set, 64-bit
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|
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// Extension
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int M : 1; // Standard Extension for Integer Multiplication/Division
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int A : 1; // Standard Extension for Atomic Instructions
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int F : 1; // Standard Extension for Single-Precision Floating-Point
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int D : 1; // Standard Extension for Double-Precision Floating-Point
|
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int Q : 1; // Standard Extension for Quad-Precision Floating-Point
|
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int C : 1; // Standard Extension for Compressed Instructions
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int Zicsr : 1; // Control and Status Register (CSR)
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int Zifencei : 1; // Instruction-Fetch Fence
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} RiscvFeatures;
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|
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typedef struct {
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RiscvFeatures features;
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char uarch[64]; // 0 terminated string
|
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char vendor[64]; // 0 terminated string
|
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} RiscvInfo;
|
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|
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typedef enum {
|
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RISCV_RV32I,
|
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RISCV_RV64I,
|
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RISCV_M,
|
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RISCV_A,
|
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RISCV_F,
|
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RISCV_D,
|
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RISCV_Q,
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RISCV_C,
|
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RISCV_Zicsr,
|
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RISCV_Zifencei,
|
||||
RISCV_LAST_,
|
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} RiscvFeaturesEnum;
|
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|
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RiscvInfo GetRiscvInfo(void);
|
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int GetRiscvFeaturesEnumValue(const RiscvFeatures* features,
|
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RiscvFeaturesEnum value);
|
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const char* GetRiscvFeaturesEnumName(RiscvFeaturesEnum);
|
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|
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CPU_FEATURES_END_CPP_NAMESPACE
|
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|
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#endif // CPU_FEATURES_INCLUDE_CPUINFO_RISCV_H_
|
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@ -205,15 +205,15 @@ CPU_FEATURES_START_CPP_NAMESPACE
|
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#define HWCAP_S390_SIE 4194304
|
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|
||||
// https://elixir.bootlin.com/linux/latest/source/arch/riscv/include/uapi/asm/hwcap.h
|
||||
#define RISCV_HWCAP_A (1UL << ('A' - 'A'))
|
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#define RISCV_HWCAP_C (1UL << ('C' - 'A'))
|
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#define RISCV_HWCAP_D (1UL << ('D' - 'A'))
|
||||
#define RISCV_HWCAP_E (1UL << ('E' - 'A'))
|
||||
#define RISCV_HWCAP_F (1UL << ('F' - 'A'))
|
||||
#define RISCV_HWCAP_I (1UL << ('I' - 'A'))
|
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#define RISCV_HWCAP_32 0x32
|
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#define RISCV_HWCAP_64 0x64
|
||||
#define RISCV_HWCAP_128 0x128
|
||||
#define RISCV_HWCAP_M (1UL << ('M' - 'A'))
|
||||
#define RISCV_HWCAP_V (1UL << ('V' - 'A'))
|
||||
#define RISCV_HWCAP_A (1UL << ('A' - 'A'))
|
||||
#define RISCV_HWCAP_F (1UL << ('F' - 'A'))
|
||||
#define RISCV_HWCAP_D (1UL << ('D' - 'A'))
|
||||
#define RISCV_HWCAP_Q (1UL << ('Q' - 'A'))
|
||||
#define RISCV_HWCAP_C (1UL << ('C' - 'A'))
|
||||
|
||||
typedef struct {
|
||||
unsigned long hwcaps;
|
||||
|
||||
@ -18,8 +18,9 @@ enum Cpu
|
||||
AArch64,
|
||||
ARM,
|
||||
MIPS,
|
||||
s390x,
|
||||
POWER,
|
||||
RISCV,
|
||||
s390x,
|
||||
}
|
||||
|
||||
enum Os
|
||||
|
||||
@ -162,6 +162,14 @@ function expand_bootlin_config() {
|
||||
local -r TOOLCHAIN_URL="https://toolchains.bootlin.com/downloads/releases/toolchains/powerpc-440fp/tarballs/powerpc-440fp--glibc--stable-2021.11-1.tar.bz2"
|
||||
local -r GCC_PREFIX="powerpc"
|
||||
;;
|
||||
"riscv32")
|
||||
local -r TOOLCHAIN_URL="https://toolchains.bootlin.com/downloads/releases/toolchains/riscv32-ilp32d/tarballs/riscv32-ilp32d--glibc--bleeding-edge-2022.08-1.tar.bz2"
|
||||
local -r GCC_PREFIX="riscv32"
|
||||
;;
|
||||
"riscv64")
|
||||
local -r TOOLCHAIN_URL="https://toolchains.bootlin.com/downloads/releases/toolchains/riscv64-lp64d/tarballs/riscv64-lp64d--glibc--stable-2022.08-1.tar.bz2"
|
||||
local -r GCC_PREFIX="riscv64"
|
||||
;;
|
||||
"s390x")
|
||||
local -r TOOLCHAIN_URL="https://toolchains.bootlin.com/downloads/releases/toolchains/s390x-z13/tarballs/s390x-z13--glibc--stable-2022.08-1.tar.bz2"
|
||||
local -r GCC_PREFIX="s390x"
|
||||
@ -362,6 +370,7 @@ DESCRIPTION
|
||||
\t\tmips64 mips64el (codespace)
|
||||
\t\tppc (bootlin)
|
||||
\t\tppc64 ppc64le (bootlin)
|
||||
\t\triscv32 riscv64 (bootlin)
|
||||
\t\ts390x (bootlin)
|
||||
|
||||
OPTIONS
|
||||
@ -448,6 +457,12 @@ function main() {
|
||||
ppc)
|
||||
expand_bootlin_config
|
||||
declare -r QEMU_ARCH=ppc ;;
|
||||
riscv32)
|
||||
expand_bootlin_config
|
||||
declare -r QEMU_ARCH=riscv32 ;;
|
||||
riscv64)
|
||||
expand_bootlin_config
|
||||
declare -r QEMU_ARCH=riscv64 ;;
|
||||
s390x)
|
||||
expand_bootlin_config
|
||||
declare -r QEMU_ARCH=s390x ;;
|
||||
|
||||
110
src/impl_riscv_linux.c
Normal file
110
src/impl_riscv_linux.c
Normal file
@ -0,0 +1,110 @@
|
||||
// Copyright 2022 Google LLC
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#include "cpu_features_macros.h"
|
||||
|
||||
#ifdef CPU_FEATURES_ARCH_RISCV
|
||||
#if defined(CPU_FEATURES_OS_LINUX)
|
||||
|
||||
#include "cpuinfo_riscv.h"
|
||||
|
||||
// According to
|
||||
// https://elixir.bootlin.com/linux/latest/source/Documentation/devicetree/bindings/riscv/cpus.yaml
|
||||
// isa string should match the following regex
|
||||
// ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:_[hsxz](?:[a-z])+)*$
|
||||
//
|
||||
// This means we can test for features in this exact order except for Z
|
||||
// extensions.
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Definitions for introspection.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#define INTROSPECTION_TABLE \
|
||||
LINE(RISCV_RV32I, RV32I, "rv32i", RISCV_HWCAP_32, 0) \
|
||||
LINE(RISCV_RV64I, RV64I, "rv64i", RISCV_HWCAP_64, 0) \
|
||||
LINE(RISCV_M, M, "m", RISCV_HWCAP_M, 0) \
|
||||
LINE(RISCV_A, A, "a", RISCV_HWCAP_A, 0) \
|
||||
LINE(RISCV_F, F, "f", RISCV_HWCAP_F, 0) \
|
||||
LINE(RISCV_D, D, "d", RISCV_HWCAP_D, 0) \
|
||||
LINE(RISCV_Q, Q, "q", RISCV_HWCAP_Q, 0) \
|
||||
LINE(RISCV_C, C, "c", RISCV_HWCAP_C, 0) \
|
||||
LINE(RISCV_Zicsr, Zicsr, "_zicsr", 0, 0) \
|
||||
LINE(RISCV_Zifencei, Zifencei, "_zifencei", 0, 0)
|
||||
#define INTROSPECTION_PREFIX Riscv
|
||||
#define INTROSPECTION_ENUM_PREFIX RISCV
|
||||
#include "define_introspection_and_hwcaps.inl"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Implementation.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdio.h>
|
||||
|
||||
#include "internal/filesystem.h"
|
||||
#include "internal/stack_line_reader.h"
|
||||
|
||||
static const RiscvInfo kEmptyRiscvInfo;
|
||||
|
||||
static void HandleRiscVIsaLine(StringView line, RiscvFeatures* const features) {
|
||||
for (size_t i = 0; i < RISCV_LAST_; ++i) {
|
||||
StringView flag = str(kCpuInfoFlags[i]);
|
||||
int index_of_flag = CpuFeatures_StringView_IndexOf(line, flag);
|
||||
bool is_set = index_of_flag != -1;
|
||||
kSetters[i](features, is_set);
|
||||
if (is_set)
|
||||
line = CpuFeatures_StringView_PopFront(line, index_of_flag + flag.size);
|
||||
}
|
||||
}
|
||||
|
||||
static bool HandleRiscVLine(const LineResult result, RiscvInfo* const info) {
|
||||
StringView line = result.line;
|
||||
StringView key, value;
|
||||
if (CpuFeatures_StringView_GetAttributeKeyValue(line, &key, &value)) {
|
||||
if (CpuFeatures_StringView_IsEquals(key, str("isa"))) {
|
||||
HandleRiscVIsaLine(value, &info->features);
|
||||
} else if (CpuFeatures_StringView_IsEquals(key, str("uarch"))) {
|
||||
int index = CpuFeatures_StringView_IndexOfChar(value, ',');
|
||||
if (index == -1) return true;
|
||||
StringView vendor = CpuFeatures_StringView_KeepFront(value, index);
|
||||
StringView uarch = CpuFeatures_StringView_PopFront(value, index + 1);
|
||||
CpuFeatures_StringView_CopyString(vendor, info->vendor,
|
||||
sizeof(info->vendor));
|
||||
CpuFeatures_StringView_CopyString(uarch, info->uarch,
|
||||
sizeof(info->uarch));
|
||||
}
|
||||
}
|
||||
return !result.eof;
|
||||
}
|
||||
|
||||
static void FillProcCpuInfoData(RiscvInfo* const info) {
|
||||
const int fd = CpuFeatures_OpenFile("/proc/cpuinfo");
|
||||
if (fd >= 0) {
|
||||
StackLineReader reader;
|
||||
StackLineReader_Initialize(&reader, fd);
|
||||
for (;;) {
|
||||
if (!HandleRiscVLine(StackLineReader_NextLine(&reader), info)) break;
|
||||
}
|
||||
CpuFeatures_CloseFile(fd);
|
||||
}
|
||||
}
|
||||
|
||||
RiscvInfo GetRiscvInfo(void) {
|
||||
RiscvInfo info = kEmptyRiscvInfo;
|
||||
FillProcCpuInfoData(&info);
|
||||
return info;
|
||||
}
|
||||
|
||||
#endif // defined(CPU_FEATURES_OS_LINUX) || defined(CPU_FEATURES_OS_ANDROID)
|
||||
#endif // CPU_FEATURES_ARCH_RISCV
|
||||
@ -37,6 +37,8 @@
|
||||
#include "cpuinfo_ppc.h"
|
||||
#elif defined(CPU_FEATURES_ARCH_S390X)
|
||||
#include "cpuinfo_s390x.h"
|
||||
#elif defined(CPU_FEATURES_ARCH_RISCV)
|
||||
#include "cpuinfo_riscv.h"
|
||||
#endif
|
||||
|
||||
// Design principles
|
||||
@ -210,6 +212,9 @@ DEFINE_ADD_FLAGS(GetPPCFeaturesEnumValue, GetPPCFeaturesEnumName, PPCFeatures,
|
||||
#elif defined(CPU_FEATURES_ARCH_S390X)
|
||||
DEFINE_ADD_FLAGS(GetS390XFeaturesEnumValue, GetS390XFeaturesEnumName, S390XFeatures,
|
||||
S390X_LAST_)
|
||||
#elif defined(CPU_FEATURES_ARCH_RISCV)
|
||||
DEFINE_ADD_FLAGS(GetRiscvFeaturesEnumValue, GetRiscvFeaturesEnumName, RiscvFeatures,
|
||||
RISCV_LAST_)
|
||||
#endif
|
||||
|
||||
// Prints a json string with characters escaping.
|
||||
@ -421,6 +426,12 @@ static Node* CreateTree(void) {
|
||||
AddMapEntry(root, "model", CreateString(strings.type.platform));
|
||||
AddMapEntry(root, "# processors", CreateInt(strings.num_processors));
|
||||
AddFlags(root, &info.features);
|
||||
#elif defined(CPU_FEATURES_ARCH_RISCV)
|
||||
const RiscvInfo info = GetRiscvInfo();
|
||||
AddMapEntry(root, "arch", CreateString("risc-v"));
|
||||
AddMapEntry(root, "vendor", CreateString(info.vendor));
|
||||
AddMapEntry(root, "microarchitecture", CreateString(info.uarch));
|
||||
AddFlags(root, &info.features);
|
||||
#endif
|
||||
return root;
|
||||
}
|
||||
|
||||
@ -96,3 +96,10 @@ if(PROCESSOR_IS_S390X)
|
||||
target_link_libraries(cpuinfo_s390x_test all_libraries)
|
||||
add_test(NAME cpuinfo_s390x_test COMMAND cpuinfo_s390x_test)
|
||||
endif()
|
||||
##------------------------------------------------------------------------------
|
||||
## cpuinfo_riscv_test
|
||||
if(PROCESSOR_IS_RISCV)
|
||||
add_executable(cpuinfo_riscv_test cpuinfo_riscv_test.cc ../src/impl_riscv_linux.c)
|
||||
target_link_libraries(cpuinfo_riscv_test all_libraries)
|
||||
add_test(NAME cpuinfo_riscv_test COMMAND cpuinfo_riscv_test)
|
||||
endif()
|
||||
|
||||
156
test/cpuinfo_riscv_test.cc
Normal file
156
test/cpuinfo_riscv_test.cc
Normal file
@ -0,0 +1,156 @@
|
||||
// Copyright 2022 Google LLC
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#include "cpuinfo_riscv.h"
|
||||
|
||||
#include "filesystem_for_testing.h"
|
||||
#include "gtest/gtest.h"
|
||||
#include "hwcaps_for_testing.h"
|
||||
|
||||
namespace cpu_features {
|
||||
namespace {
|
||||
|
||||
TEST(CpuinfoRiscvTest, Sipeed_Lichee_RV_FromCpuInfo) {
|
||||
ResetHwcaps();
|
||||
auto& fs = GetEmptyFilesystem();
|
||||
fs.CreateFile("/proc/cpuinfo", R"(processor : 0
|
||||
hart : 0
|
||||
isa : rv64imafdc
|
||||
mmu : sv39
|
||||
uarch : thead,c906)");
|
||||
const auto info = GetRiscvInfo();
|
||||
EXPECT_STREQ(info.uarch, "c906");
|
||||
EXPECT_STREQ(info.vendor, "thead");
|
||||
|
||||
EXPECT_FALSE(info.features.RV32I);
|
||||
EXPECT_TRUE(info.features.RV64I);
|
||||
EXPECT_TRUE(info.features.M);
|
||||
EXPECT_TRUE(info.features.A);
|
||||
EXPECT_TRUE(info.features.F);
|
||||
EXPECT_TRUE(info.features.D);
|
||||
EXPECT_FALSE(info.features.Q);
|
||||
EXPECT_TRUE(info.features.C);
|
||||
}
|
||||
|
||||
// https://github.com/ThomasKaiser/sbc-bench/blob/284e82b016ec1beeac42a5fcbe556b670f68441a/results/Kendryte-K510-4.17.0.cpuinfo
|
||||
TEST(CpuinfoRiscvTest, Kendryte_K510_FromCpuInfo) {
|
||||
ResetHwcaps();
|
||||
auto& fs = GetEmptyFilesystem();
|
||||
fs.CreateFile("/proc/cpuinfo", R"(
|
||||
hart : 0
|
||||
isa : rv64i2p0m2p0a2p0f2p0d2p0c2p0xv5-0p0
|
||||
mmu : sv39
|
||||
|
||||
hart : 1
|
||||
isa : rv64i2p0m2p0a2p0f2p0d2p0c2p0xv5-0p0
|
||||
mmu : sv39");
|
||||
const auto info = GetRiscvInfo();
|
||||
EXPECT_STREQ(info.uarch, "");
|
||||
EXPECT_STREQ(info.vendor, "");
|
||||
|
||||
EXPECT_FALSE(info.features.RV32I);
|
||||
EXPECT_TRUE(info.features.RV64I);
|
||||
EXPECT_TRUE(info.features.M);
|
||||
EXPECT_TRUE(info.features.A);
|
||||
EXPECT_TRUE(info.features.F);
|
||||
EXPECT_TRUE(info.features.D);
|
||||
EXPECT_FALSE(info.features.Q);
|
||||
EXPECT_TRUE(info.features.C);
|
||||
}
|
||||
|
||||
// https://github.com/ThomasKaiser/sbc-bench/blob/284e82b016ec1beeac42a5fcbe556b670f68441a/results/T-Head-C910-5.10.4.cpuinfo
|
||||
TEST(CpuinfoRiscvTest, T_Head_C910_FromCpuInfo) {
|
||||
ResetHwcaps();
|
||||
auto& fs = GetEmptyFilesystem();
|
||||
fs.CreateFile("/proc/cpuinfo", R"(
|
||||
processor : 0
|
||||
hart : 0
|
||||
isa : rv64imafdcsu
|
||||
mmu : sv39
|
||||
cpu-freq : 1.2Ghz
|
||||
cpu-icache : 64KB
|
||||
cpu-dcache : 64KB
|
||||
cpu-l2cache : 2MB
|
||||
cpu-tlb : 1024 4-ways
|
||||
cpu-cacheline : 64Bytes
|
||||
cpu-vector : 0.7.1
|
||||
|
||||
processor : 1
|
||||
hart : 1
|
||||
isa : rv64imafdcsu
|
||||
mmu : sv39
|
||||
cpu-freq : 1.2Ghz
|
||||
cpu-icache : 64KB
|
||||
cpu-dcache : 64KB
|
||||
cpu-l2cache : 2MB
|
||||
cpu-tlb : 1024 4-ways
|
||||
cpu-cacheline : 64Bytes
|
||||
cpu-vector : 0.7.1");
|
||||
const auto info = GetRiscvInfo();
|
||||
EXPECT_STREQ(info.uarch, "");
|
||||
EXPECT_STREQ(info.vendor, "");
|
||||
|
||||
EXPECT_FALSE(info.features.RV32I);
|
||||
EXPECT_TRUE(info.features.RV64I);
|
||||
EXPECT_TRUE(info.features.M);
|
||||
EXPECT_TRUE(info.features.A);
|
||||
EXPECT_TRUE(info.features.F);
|
||||
EXPECT_TRUE(info.features.D);
|
||||
EXPECT_FALSE(info.features.Q);
|
||||
EXPECT_TRUE(info.features.C);
|
||||
}
|
||||
|
||||
TEST(CpuinfoRiscvTest, UnknownFromCpuInfo) {
|
||||
ResetHwcaps();
|
||||
auto& fs = GetEmptyFilesystem();
|
||||
fs.CreateFile("/proc/cpuinfo", R"(
|
||||
processor : 0
|
||||
hart : 2
|
||||
isa : rv64imafdc
|
||||
mmu : sv39
|
||||
uarch : sifive,bullet0
|
||||
|
||||
processor : 1
|
||||
hart : 1
|
||||
isa : rv64imafdc
|
||||
mmu : sv39
|
||||
uarch : sifive,bullet0
|
||||
|
||||
processor : 2
|
||||
hart : 3
|
||||
isa : rv64imafdc
|
||||
mmu : sv39
|
||||
uarch : sifive,bullet0
|
||||
|
||||
processor : 3
|
||||
hart : 4
|
||||
isa : rv64imafdc
|
||||
mmu : sv39
|
||||
uarch : sifive,bullet0)");
|
||||
const auto info = GetRiscvInfo();
|
||||
EXPECT_STREQ(info.uarch, "bullet0");
|
||||
EXPECT_STREQ(info.vendor, "sifive");
|
||||
|
||||
EXPECT_FALSE(info.features.RV32I);
|
||||
EXPECT_TRUE(info.features.RV64I);
|
||||
EXPECT_TRUE(info.features.M);
|
||||
EXPECT_TRUE(info.features.A);
|
||||
EXPECT_TRUE(info.features.F);
|
||||
EXPECT_TRUE(info.features.D);
|
||||
EXPECT_FALSE(info.features.Q);
|
||||
EXPECT_TRUE(info.features.C);
|
||||
}
|
||||
|
||||
} // namespace
|
||||
} // namespace cpu_features
|
||||
Loading…
x
Reference in New Issue
Block a user