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Support risc-v (#287)
Co-authored-by: DaniAffCH <danieleaffinita2000@gmail.com> Co-authored-by: Corentin Le Molgat <corentinl@google.com>
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@ -205,15 +205,15 @@ CPU_FEATURES_START_CPP_NAMESPACE
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#define HWCAP_S390_SIE 4194304
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// https://elixir.bootlin.com/linux/latest/source/arch/riscv/include/uapi/asm/hwcap.h
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#define RISCV_HWCAP_A (1UL << ('A' - 'A'))
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#define RISCV_HWCAP_C (1UL << ('C' - 'A'))
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#define RISCV_HWCAP_D (1UL << ('D' - 'A'))
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#define RISCV_HWCAP_E (1UL << ('E' - 'A'))
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#define RISCV_HWCAP_F (1UL << ('F' - 'A'))
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#define RISCV_HWCAP_I (1UL << ('I' - 'A'))
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#define RISCV_HWCAP_32 0x32
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#define RISCV_HWCAP_64 0x64
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#define RISCV_HWCAP_128 0x128
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#define RISCV_HWCAP_M (1UL << ('M' - 'A'))
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#define RISCV_HWCAP_V (1UL << ('V' - 'A'))
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#define RISCV_HWCAP_A (1UL << ('A' - 'A'))
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#define RISCV_HWCAP_F (1UL << ('F' - 'A'))
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#define RISCV_HWCAP_D (1UL << ('D' - 'A'))
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#define RISCV_HWCAP_Q (1UL << ('Q' - 'A'))
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#define RISCV_HWCAP_C (1UL << ('C' - 'A'))
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typedef struct {
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unsigned long hwcaps;
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