mirror of
https://github.com/google/cpu_features.git
synced 2025-04-27 23:22:31 +02:00
Update features for AArch64.
Add all missing features up to Linux v5.0. Features added: evtstrm, atomics, fphp, asimdhp, cpuid, asimdrdm, jscvt, fcma, lrcpc, dcpop, sha3, sm3, sm4, asimddp, sha512, sve, asimdfhm, dit, uscat, ilrcpc, flagm, ssbs, sb, paca, pacg.
This commit is contained in:
Tamas Zsoldos
parent
b9593c8b39
commit
d835b4958c
@ -21,13 +21,38 @@
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CPU_FEATURES_START_CPP_NAMESPACE
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typedef struct {
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int fp : 1; // Floating-point.
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int asimd : 1; // Advanced SIMD.
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int aes : 1; // Hardware-accelerated Advanced Encryption Standard.
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int pmull : 1; // Polynomial multiply long.
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int sha1 : 1; // Hardware-accelerated SHA1.
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int sha2 : 1; // Hardware-accelerated SHA2-256.
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int crc32 : 1; // Hardware-accelerated CRC-32.
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int fp : 1; // Floating-point.
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int asimd : 1; // Advanced SIMD.
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int evtstrm : 1; // Generic timer generated events.
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int aes : 1; // Hardware-accelerated Advanced Encryption Standard.
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int pmull : 1; // Polynomial multiply long.
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int sha1 : 1; // Hardware-accelerated SHA1.
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int sha2 : 1; // Hardware-accelerated SHA2-256.
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int crc32 : 1; // Hardware-accelerated CRC-32.
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int atomics : 1; // Armv8.1 atomic instructions.
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int fphp : 1; // Half-precision floating point support.
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int asimdhp : 1; // Advanced SIMD half-precision support.
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int cpuid : 1; // Access to certain ID registers.
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int asimdrdm : 1; // Rounding Double Multiply Accumulate/Subtract.
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int jscvt : 1; // Support for JavaScript conversion.
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int fcma : 1; // Floating point complex numbers.
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int lrcpc : 1; // Support for weaker release consistency.
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int dcpop : 1; // Data persistence writeback.
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int sha3 : 1; // Hardware-accelerated SHA3.
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int sm3 : 1; // Hardware-accelerated SM3.
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int sm4 : 1; // Hardware-accelerated SM4.
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int asimddp : 1; // Dot product instruction.
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int sha512 : 1; // Hardware-accelerated SHA512.
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int sve : 1; // Scalable Vector Extension.
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int asimdfhm : 1; // Additional half-precision instructions.
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int dit : 1; // Data independent timing.
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int uscat : 1; // Unaligned atomics support.
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int ilrcpc : 1; // Additional support for weaker release consistency.
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int flagm : 1; // Flag manipulation instructions.
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int ssbs : 1; // Speculative Store Bypass Safe PSTATE bit.
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int sb : 1; // Speculation barrier.
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int paca : 1; // Address authentication.
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int pacg : 1; // Generic authentication.
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// Make sure to update Aarch64FeaturesEnum below if you add a field here.
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} Aarch64Features;
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@ -48,11 +73,36 @@ Aarch64Info GetAarch64Info(void);
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typedef enum {
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AARCH64_FP,
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AARCH64_ASIMD,
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AARCH64_EVTSTRM,
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AARCH64_AES,
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AARCH64_PMULL,
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AARCH64_SHA1,
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AARCH64_SHA2,
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AARCH64_CRC32,
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AARCH64_ATOMICS,
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AARCH64_FPHP,
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AARCH64_ASIMDHP,
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AARCH64_CPUID,
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AARCH64_ASIMDRDM,
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AARCH64_JSCVT,
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AARCH64_FCMA,
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AARCH64_LRCPC,
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AARCH64_DCPOP,
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AARCH64_SHA3,
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AARCH64_SM3,
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AARCH64_SM4,
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AARCH64_ASIMDDP,
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AARCH64_SHA512,
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AARCH64_SVE,
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AARCH64_ASIMDFHM,
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AARCH64_DIT,
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AARCH64_USCAT,
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AARCH64_ILRCPC,
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AARCH64_FLAGM,
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AARCH64_SSBS,
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AARCH64_SB,
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AARCH64_PACA,
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AARCH64_PACG,
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AARCH64_LAST_,
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} Aarch64FeaturesEnum;
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@ -28,11 +28,36 @@ CPU_FEATURES_START_CPP_NAMESPACE
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// http://elixir.free-electrons.com/linux/latest/source/arch/arm64/include/uapi/asm/hwcap.h
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#define AARCH64_HWCAP_FP (1UL << 0)
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#define AARCH64_HWCAP_ASIMD (1UL << 1)
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#define AARCH64_HWCAP_EVTSTRM (1UL << 2)
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#define AARCH64_HWCAP_AES (1UL << 3)
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#define AARCH64_HWCAP_PMULL (1UL << 4)
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#define AARCH64_HWCAP_SHA1 (1UL << 5)
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#define AARCH64_HWCAP_SHA2 (1UL << 6)
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#define AARCH64_HWCAP_CRC32 (1UL << 7)
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#define AARCH64_HWCAP_ATOMICS (1UL << 8)
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#define AARCH64_HWCAP_FPHP (1UL << 9)
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#define AARCH64_HWCAP_ASIMDHP (1UL << 10)
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#define AARCH64_HWCAP_CPUID (1UL << 11)
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#define AARCH64_HWCAP_ASIMDRDM (1UL << 12)
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#define AARCH64_HWCAP_JSCVT (1UL << 13)
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#define AARCH64_HWCAP_FCMA (1UL << 14)
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#define AARCH64_HWCAP_LRCPC (1UL << 15)
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#define AARCH64_HWCAP_DCPOP (1UL << 16)
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#define AARCH64_HWCAP_SHA3 (1UL << 17)
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#define AARCH64_HWCAP_SM3 (1UL << 18)
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#define AARCH64_HWCAP_SM4 (1UL << 19)
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#define AARCH64_HWCAP_ASIMDDP (1UL << 20)
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#define AARCH64_HWCAP_SHA512 (1UL << 21)
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#define AARCH64_HWCAP_SVE (1UL << 22)
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#define AARCH64_HWCAP_ASIMDFHM (1UL << 23)
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#define AARCH64_HWCAP_DIT (1UL << 24)
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#define AARCH64_HWCAP_USCAT (1UL << 25)
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#define AARCH64_HWCAP_ILRCPC (1UL << 26)
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#define AARCH64_HWCAP_FLAGM (1UL << 27)
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#define AARCH64_HWCAP_SSBS (1UL << 28)
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#define AARCH64_HWCAP_SB (1UL << 29)
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#define AARCH64_HWCAP_PACA (1UL << 30)
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#define AARCH64_HWCAP_PACG (1UL << 31)
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// http://elixir.free-electrons.com/linux/latest/source/arch/arm/include/uapi/asm/hwcap.h
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#define ARM_HWCAP_SWP (1UL << 0)
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@ -25,20 +25,70 @@
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DECLARE_SETTER(Aarch64Features, fp)
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DECLARE_SETTER(Aarch64Features, asimd)
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DECLARE_SETTER(Aarch64Features, evtstrm)
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DECLARE_SETTER(Aarch64Features, aes)
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DECLARE_SETTER(Aarch64Features, pmull)
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DECLARE_SETTER(Aarch64Features, sha1)
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DECLARE_SETTER(Aarch64Features, sha2)
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DECLARE_SETTER(Aarch64Features, crc32)
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DECLARE_SETTER(Aarch64Features, atomics)
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DECLARE_SETTER(Aarch64Features, fphp)
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DECLARE_SETTER(Aarch64Features, asimdhp)
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DECLARE_SETTER(Aarch64Features, cpuid)
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DECLARE_SETTER(Aarch64Features, asimdrdm)
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DECLARE_SETTER(Aarch64Features, jscvt)
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DECLARE_SETTER(Aarch64Features, fcma)
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DECLARE_SETTER(Aarch64Features, lrcpc)
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DECLARE_SETTER(Aarch64Features, dcpop)
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DECLARE_SETTER(Aarch64Features, sha3)
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DECLARE_SETTER(Aarch64Features, sm3)
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DECLARE_SETTER(Aarch64Features, sm4)
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DECLARE_SETTER(Aarch64Features, asimddp)
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DECLARE_SETTER(Aarch64Features, sha512)
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DECLARE_SETTER(Aarch64Features, sve)
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DECLARE_SETTER(Aarch64Features, asimdfhm)
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DECLARE_SETTER(Aarch64Features, dit)
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DECLARE_SETTER(Aarch64Features, uscat)
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DECLARE_SETTER(Aarch64Features, ilrcpc)
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DECLARE_SETTER(Aarch64Features, flagm)
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DECLARE_SETTER(Aarch64Features, ssbs)
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DECLARE_SETTER(Aarch64Features, sb)
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DECLARE_SETTER(Aarch64Features, paca)
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DECLARE_SETTER(Aarch64Features, pacg)
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static const CapabilityConfig kConfigs[] = {
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[AARCH64_FP] = {{AARCH64_HWCAP_FP, 0}, "fp", &set_fp}, //
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[AARCH64_ASIMD] = {{AARCH64_HWCAP_ASIMD, 0}, "asimd", &set_asimd}, //
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[AARCH64_AES] = {{AARCH64_HWCAP_AES, 0}, "aes", &set_aes}, //
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[AARCH64_PMULL] = {{AARCH64_HWCAP_PMULL, 0}, "pmull", &set_pmull}, //
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[AARCH64_SHA1] = {{AARCH64_HWCAP_SHA1, 0}, "sha1", &set_sha1}, //
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[AARCH64_SHA2] = {{AARCH64_HWCAP_SHA2, 0}, "sha2", &set_sha2}, //
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[AARCH64_CRC32] {{AARCH64_HWCAP_CRC32, 0}, "crc32", &set_crc32}, //
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[AARCH64_FP] = {{AARCH64_HWCAP_FP, 0}, "fp", &set_fp},
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[AARCH64_ASIMD] = {{AARCH64_HWCAP_ASIMD, 0}, "asimd", &set_asimd},
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[AARCH64_EVTSTRM] = {{AARCH64_HWCAP_EVTSTRM, 0}, "evtstrm", &set_evtstrm},
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[AARCH64_AES] = {{AARCH64_HWCAP_AES, 0}, "aes", &set_aes},
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[AARCH64_PMULL] = {{AARCH64_HWCAP_PMULL, 0}, "pmull", &set_pmull},
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[AARCH64_SHA1] = {{AARCH64_HWCAP_SHA1, 0}, "sha1", &set_sha1},
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[AARCH64_SHA2] = {{AARCH64_HWCAP_SHA2, 0}, "sha2", &set_sha2},
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[AARCH64_CRC32] = {{AARCH64_HWCAP_CRC32, 0}, "crc32", &set_crc32},
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[AARCH64_ATOMICS] = {{AARCH64_HWCAP_ATOMICS, 0}, "atomics", &set_atomics},
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[AARCH64_FPHP] = {{AARCH64_HWCAP_FPHP, 0}, "fphp", &set_fphp},
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[AARCH64_ASIMDHP] = {{AARCH64_HWCAP_ASIMDHP, 0}, "asimdhp", &set_asimdhp},
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[AARCH64_CPUID] = {{AARCH64_HWCAP_CPUID, 0}, "cpuid", &set_cpuid},
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[AARCH64_ASIMDRDM] = {{AARCH64_HWCAP_ASIMDRDM, 0}, "asimdrdm", &set_asimdrdm},
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[AARCH64_JSCVT] = {{AARCH64_HWCAP_JSCVT, 0}, "jscvt", &set_jscvt},
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[AARCH64_FCMA] = {{AARCH64_HWCAP_FCMA, 0}, "fcma", &set_fcma},
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[AARCH64_LRCPC] = {{AARCH64_HWCAP_LRCPC, 0}, "lrcpc", &set_lrcpc},
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[AARCH64_DCPOP] = {{AARCH64_HWCAP_DCPOP, 0}, "dcpop", &set_dcpop},
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[AARCH64_SHA3] = {{AARCH64_HWCAP_SHA3, 0}, "sha3", &set_sha3},
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[AARCH64_SM3] = {{AARCH64_HWCAP_SM3, 0}, "sm3", &set_sm3},
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[AARCH64_SM4] = {{AARCH64_HWCAP_SM4, 0}, "sm4", &set_sm4},
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[AARCH64_ASIMDDP] = {{AARCH64_HWCAP_ASIMDDP, 0}, "asimddp", &set_asimddp},
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[AARCH64_SHA512] = {{AARCH64_HWCAP_SHA512, 0}, "sha512", &set_sha512},
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[AARCH64_SVE] = {{AARCH64_HWCAP_SVE, 0}, "sve", &set_sve},
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[AARCH64_ASIMDFHM] = {{AARCH64_HWCAP_ASIMDFHM, 0}, "asimdfhm", &set_asimdfhm},
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[AARCH64_DIT] = {{AARCH64_HWCAP_DIT, 0}, "dit", &set_dit},
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[AARCH64_USCAT] = {{AARCH64_HWCAP_USCAT, 0}, "uscat", &set_uscat},
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[AARCH64_ILRCPC] = {{AARCH64_HWCAP_ILRCPC, 0}, "ilrcpc", &set_ilrcpc},
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[AARCH64_FLAGM] = {{AARCH64_HWCAP_FLAGM, 0}, "flagm", &set_flagm},
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[AARCH64_SSBS] = {{AARCH64_HWCAP_SSBS, 0}, "ssbs", &set_ssbs},
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[AARCH64_SB] = {{AARCH64_HWCAP_SB, 0}, "sb", &set_sb},
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[AARCH64_PACA] = {{AARCH64_HWCAP_PACA, 0}, "paca", &set_paca},
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[AARCH64_PACG] = {{AARCH64_HWCAP_PACG, 0}, "pacg", &set_pacg},
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};
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static const size_t kConfigsSize = sizeof(kConfigs) / sizeof(CapabilityConfig);
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@ -105,6 +155,8 @@ int GetAarch64FeaturesEnumValue(const Aarch64Features* features,
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return features->fp;
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case AARCH64_ASIMD:
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return features->asimd;
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case AARCH64_EVTSTRM:
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return features->evtstrm;
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case AARCH64_AES:
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return features->aes;
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case AARCH64_PMULL:
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@ -115,6 +167,54 @@ int GetAarch64FeaturesEnumValue(const Aarch64Features* features,
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return features->sha2;
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case AARCH64_CRC32:
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return features->crc32;
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case AARCH64_ATOMICS:
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return features->atomics;
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case AARCH64_FPHP:
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return features->fphp;
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case AARCH64_ASIMDHP:
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return features->asimdhp;
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case AARCH64_CPUID:
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return features->cpuid;
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case AARCH64_ASIMDRDM:
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return features->asimdrdm;
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case AARCH64_JSCVT:
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return features->jscvt;
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case AARCH64_FCMA:
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return features->fcma;
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case AARCH64_LRCPC:
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return features->lrcpc;
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case AARCH64_DCPOP:
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return features->dcpop;
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case AARCH64_SHA3:
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return features->sha3;
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case AARCH64_SM3:
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return features->sm3;
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case AARCH64_SM4:
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return features->sm4;
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case AARCH64_ASIMDDP:
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return features->asimddp;
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case AARCH64_SHA512:
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return features->sha512;
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case AARCH64_SVE:
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return features->sve;
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case AARCH64_ASIMDFHM:
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return features->asimdfhm;
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case AARCH64_DIT:
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return features->dit;
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case AARCH64_USCAT:
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return features->uscat;
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case AARCH64_ILRCPC:
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return features->ilrcpc;
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case AARCH64_FLAGM:
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return features->flagm;
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case AARCH64_SSBS:
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return features->ssbs;
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case AARCH64_SB:
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return features->sb;
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case AARCH64_PACA:
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return features->paca;
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case AARCH64_PACG:
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return features->pacg;
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case AARCH64_LAST_:
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break;
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}
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@ -29,11 +29,36 @@ TEST(CpuinfoAarch64Test, FromHardwareCap) {
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const auto info = GetAarch64Info();
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EXPECT_TRUE(info.features.fp);
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EXPECT_FALSE(info.features.asimd);
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EXPECT_FALSE(info.features.evtstrm);
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EXPECT_TRUE(info.features.aes);
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EXPECT_FALSE(info.features.pmull);
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EXPECT_FALSE(info.features.sha1);
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EXPECT_FALSE(info.features.sha2);
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EXPECT_FALSE(info.features.crc32);
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EXPECT_FALSE(info.features.atomics);
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EXPECT_FALSE(info.features.fphp);
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EXPECT_FALSE(info.features.asimdhp);
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EXPECT_FALSE(info.features.cpuid);
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EXPECT_FALSE(info.features.asimdrdm);
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EXPECT_FALSE(info.features.jscvt);
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EXPECT_FALSE(info.features.fcma);
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EXPECT_FALSE(info.features.lrcpc);
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EXPECT_FALSE(info.features.dcpop);
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EXPECT_FALSE(info.features.sha3);
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EXPECT_FALSE(info.features.sm3);
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EXPECT_FALSE(info.features.sm4);
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EXPECT_FALSE(info.features.asimddp);
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EXPECT_FALSE(info.features.sha512);
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EXPECT_FALSE(info.features.sve);
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EXPECT_FALSE(info.features.asimdfhm);
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EXPECT_FALSE(info.features.dit);
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EXPECT_FALSE(info.features.uscat);
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EXPECT_FALSE(info.features.ilrcpc);
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EXPECT_FALSE(info.features.flagm);
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EXPECT_FALSE(info.features.ssbs);
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EXPECT_FALSE(info.features.sb);
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EXPECT_FALSE(info.features.paca);
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EXPECT_FALSE(info.features.pacg);
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}
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TEST(CpuinfoAarch64Test, ARMCortexA53) {
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@ -63,11 +88,37 @@ CPU revision : 3)");
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EXPECT_TRUE(info.features.fp);
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EXPECT_TRUE(info.features.asimd);
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EXPECT_TRUE(info.features.evtstrm);
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EXPECT_TRUE(info.features.aes);
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EXPECT_TRUE(info.features.pmull);
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EXPECT_TRUE(info.features.sha1);
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EXPECT_TRUE(info.features.sha2);
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EXPECT_TRUE(info.features.crc32);
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EXPECT_FALSE(info.features.atomics);
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EXPECT_FALSE(info.features.fphp);
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EXPECT_FALSE(info.features.asimdhp);
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EXPECT_FALSE(info.features.cpuid);
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EXPECT_FALSE(info.features.asimdrdm);
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EXPECT_FALSE(info.features.jscvt);
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EXPECT_FALSE(info.features.fcma);
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EXPECT_FALSE(info.features.lrcpc);
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EXPECT_FALSE(info.features.dcpop);
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EXPECT_FALSE(info.features.sha3);
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EXPECT_FALSE(info.features.sm3);
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EXPECT_FALSE(info.features.sm4);
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EXPECT_FALSE(info.features.asimddp);
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EXPECT_FALSE(info.features.sha512);
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EXPECT_FALSE(info.features.sve);
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EXPECT_FALSE(info.features.asimdfhm);
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EXPECT_FALSE(info.features.dit);
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EXPECT_FALSE(info.features.uscat);
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EXPECT_FALSE(info.features.ilrcpc);
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EXPECT_FALSE(info.features.flagm);
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EXPECT_FALSE(info.features.ssbs);
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EXPECT_FALSE(info.features.sb);
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EXPECT_FALSE(info.features.paca);
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EXPECT_FALSE(info.features.pacg);
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}
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} // namespace
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