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432 Commits 2 Branches 12 Tags
6516495ce9041d61deac40e50feb87330b24e847
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50 Commits

Author SHA1 Message Date
Mykola Hohsadze
b960bcf0f5 Add ZEN2 4800S 0880F40 (#331) 2023-09-05 14:14:53 +02:00
Mykola Hohsadze
aeaa84ecf4 Add Intel Alder Lake N detection (#330) 2023-09-05 14:14:21 +02:00
Mykola Hohsadze
248aa1b938 Add AMD ZEN4 Genoa detection (#329) 2023-09-05 14:13:54 +02:00
Mykola Hohsadze
199d299ce5 Add ZEN4 Phoenix detection (#328) 2023-09-05 14:13:27 +02:00
Tomahawkd
b5cb91b35c Add Intel LAM/AMD UAI feature detection in X86_64 (#315) 
* Add Intel LAM/AMD UAI features in X86

* Add AMD UAI test for AMD_K19_ZEN4_RAPHAEL

* Add separate UAI for AMD
 2023-08-28 16:25:24 +02:00
Mykola Hohsadze
0e9da93fac Add Mendocino ZEN2 detection (#305) 2023-04-25 10:11:23 +02:00
Mykola Hohsadze
5607a689e0 Add Raptor Lake-P and Raptor Lake-HX/S detection (#300) 2023-03-06 15:04:00 +01:00
Mykola Hohsadze
19799486d2 Add Intel Raptor Lake uarch detection (#283) 2022-11-08 15:35:50 +01:00
Mykola Hohsadze
bddcc3721c Add REP instructions detection (#282) 2022-10-26 16:13:15 +02:00
Mykola Hohsadze
26852665b4 Add X86 movdir detection (#281) 2022-10-25 09:33:13 +02:00
Mykola Hohsdze
3485a46a6d Add X86 GFNI detection 2022-10-24 08:29:55 +02:00
damageboy
8ca7c65f65 add x86/avx512_fp16 detection (#279) 
fixes #278
 2022-10-20 11:26:13 +02:00
Mykola Hohsadze
627959faee Add AMD ZEN4 Raphael detection (#277) 2022-10-19 11:36:27 +02:00
Andrei Kurushin
4760834428 add mobile core flavor (#266) 2022-10-19 11:35:19 +02:00
Mykola Hohsadze
302566b160 Replace hardcoded cache type value to enum type for X86 tests (#270) 
Replaced hardcoded integer values of cache type to `CacheType` values for X86 tests and added declaration `CacheType` for `P4_CacheInfo` test
 2022-09-19 12:56:09 +02:00
William Tambellini
b69591add3 Add support for detecting Intel CascadeLake CPUs (#271) 
Should close
https://github.com/google/cpu_features/issues/260
 2022-09-19 10:00:01 +02:00
Mykola Hohsadze
cee2648cf0 Add cache detection for old AMD processors (#199) 
* Add cache detection for of old AMD processors




update links

* Add documentation link for cache_size * 512

* Update legacy amd cache detection
 2022-08-18 13:55:21 +02:00
Andrei Kurushin
1e253a7728 add amd cato (#267) 
* add AMD RX-8125, RX-8120, and A9-9820 detection
 2022-08-18 10:40:24 +02:00
Andrei Kurushin
4e8d2e3a22 add intel goldmont plus (#256) 
* add intel goldmont plus (INTEL_ATOM_GMT_PLUS)
 2022-08-08 09:27:18 +02:00
Andrei Kurushin
876b9e6a73 add amd piledriver 0x10 model (#255) 
* add amd piledriver 0x10 model
 2022-08-05 15:56:53 +02:00
Andrew Kurushin
349ef06634 add CometLake model 166 2022-08-05 15:55:18 +02:00
Mykola Hohsdze
cf7cd9824f Replace hardcode values to constants 2022-08-05 09:02:13 +02:00
Mykola Hohsdze
c6b0a803a8 Add AVX_VNNI 2022-08-04 21:56:32 +02:00
Andrew Kurushin
cbc8f9c7a3 add Lakefield 2022-08-04 21:54:23 +02:00
Andrew Kurushin
6d62f2fa64 add intel Tremont microarch 2022-08-04 21:54:23 +02:00
Andrei Kurushin
d3c5e369db test enum macro consistency (#257) 2022-07-28 12:34:42 +02:00
Mykola Hohsadze
601471d527 Add detection LZCNT (#254) 
Fixes #253
 2022-07-28 12:22:16 +02:00
Andrei Kurushin
677d6419b2 remove internal FillX86BrandString usage (#258) 2022-07-25 17:39:50 +02:00
Andrei Kurushin
c1620a979e add comet lake unit test #248 (#250) 2022-07-21 21:57:38 +02:00
Andrei Kurushin
38ae5d095c add windows ssse3,sse4_1,sse4_2 detection for non avx path (#251) 
* add windows ssse3,sse4_1,sse4_2 detection for non avx path

* remove special WESTMERE case

* move windows conditional redefinition to separate header

* fix minor issues
 2022-07-21 21:56:50 +02:00
Mykola Hohsadze
3c4801d12d Add AMD ZEN 4 uarch and update detection (#243) 
* Add AMD ZEN 4 uarch and update detection

* Add tests via cpuid dump
 2022-06-17 11:18:05 +02:00
jmfriedt
40e1c7158d replace sse3 detection with pni when reading /proc/cpuinfo (#225) 2022-02-22 14:19:17 +01:00
Mykola Hohsadze
f1801f0ca1 Fix list_cpu_features.exe does not detect SSE42 on Xeon X5650 (Windows) (#220) 2022-01-31 10:15:17 +01:00
Guillaume Chatelet
149916384b [x86] Embed brand_string and mark FillX86BrandString as deprecated (#214) 2022-01-14 17:20:31 +01:00
Nikolay Hohsadze
5695cc4817 Update uarch detection for Intel processors (#184) 2021-10-29 10:41:50 +02:00
Guillaume Chatelet
deb2a61b80 New code layout - breaking change in cpu_features_macros.h (#194) 
This commit helps with platform code separation (fixes #3). It should also help with the build as we can simply include all `impl_*.c` files regardless of OS / arch.

Note: this patch contains breaking changes in `include/cpu_features_macros.h`
 - `CPU_FEATURES_OS_LINUX_OR_ANDROID` does not exist anymore
 - `CPU_FEATURES_OS_FREEBSD`, `CPU_FEATURES_OS_ANDROID` and `CPU_FEATURES_OS_LINUX` are now mutually exclusive (i.e. `CPU_FEATURES_OS_ANDROID` does not imply `CPU_FEATURES_OS_LINUX`)
 - `CPU_FEATURES_OS_DARWIN` has been renamed into `CPU_FEATURES_OS_MACOS` to be able to target non-Mac Apple products (IOS, TV, WATCH). They are now targetable with `CPU_FEATURES_OS_IPHONE`. This matches Apple naming convention described in [this stackoverflow](https://stackoverflow.com/a/49560690).
 2021-10-28 13:52:46 +02:00
Guillaume Chatelet
32b49eb5e7 Fixes wrong cache detection of old processors (#183) 2021-10-20 17:02:52 +02:00
Guillaume Chatelet
4a81f3756e [NFC] encapsulate fake cpu instance in x86 test 2021-10-20 08:15:44 +00:00
Nikolay Hohsadze
0925f6953c Add cache info for new AMD CPUs (0x8000001D) (#171) 2021-10-18 14:14:29 +02:00
Guillaume Chatelet
119943707c Add support for FreeBSD on x86 (#163) 2021-07-02 15:37:03 +02:00
Nikolay Hohsadze
5492c4c561 CPU features for AMD (#165) 2021-06-30 12:38:56 +02:00
Kris Kwiatkowski
d35e2f38eb Detect Intel's Multi-Precision Add-Carry Instruction Extensions (#157) 2021-05-21 10:47:32 +02:00
Guillaume Chatelet
3cc8f310d9 [NFC] Update copyright from Google Inc. to Google LLC 2020-10-12 08:55:20 +00:00
Guillaume Chatelet
4795373db2 Fix SSE detection on non-AVX CPUs (#135) 
Fixes #4. This is based on #115 with a few modifications:
 - Removed use of __builtin_cpu_supports since it relies on cpuid and doesn't improve on the current situation,
 - Added detection for all of sse, sse2, sse3, ssse3, sse4_1 and sse4_2,
 - Added tests for Atom, Nehalem, and P3 processors,

Thx to @gadoofou87 for providing the original PR.
It also removes the need for #92

* Fix SSE detection on non-AVX CPUs
* Fixes typo
* Mock OSX sysctlbyname in tests
* Also update other tests
* FakeCpu is reset between each tests
* Fix conflicting name on Windows
* Disable pre AVX cpu sse detection tests on Windows
* Guard OS specific code with macros
* Fix missing import for tests
* Fix wrong function prototype
* Fix wrong mocking of P3 on Windows
* Completely guard OS specific parts in x86 tests
* Store DWORD instead unsigned long for x86 tests
 2020-10-09 15:20:25 +00:00
Guillaume Chatelet
22a5362e11 [NFC] clang-format codebase (#134) 
* [NFC] clang-format codebase

* revert to 80 char columns at the price of uglier table init

* Specifically disabling clang-format for table initialization
 2020-09-23 09:52:20 +00:00
Jeff Hammond
33bd72c1bc detect future Intel AVX/AMX features (#124) 
* add Ice Lake Server and Sapphire Rapids models

The information contained in this commit was obtained from
"Intel® Architecture Instruction Set Extensions and Future Features Programming Reference" document 319433-040 from
https://software.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html

Signed-off-by: Jeff Hammond <jeff.r.hammond@intel.com>

* Tiger Lake; Ice Lake NNP-I; SPR string

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* add AVX512_BF16 and AVX512_VP2INTERSECT detection

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* correction for KNM features: s/4VBMI2/4FMAPS/g

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* add AMX/TMUL bits from 319433-040

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* add Intel copyright

Fixes #128
 2020-09-21 07:56:26 +00:00
Artem Alekseev
653d581e03 Add support for leaf2 and leaf4 on Intel's x86 arch (#80) 
* Add support for leaf4 on Intel's x86 arch
* Update cpuinfo_x86.h
* Fix typo
* Force compiler to use C99
* Add Intel x86 leaf2 support
* Fixes after review
* Fix review comments
 2019-07-02 16:52:25 +02:00
Artem Alekseev
bfb4cf99cc Add CpuIdEx function to pass inputs in ecx register (required for E.g. leaf4) (#77) 2019-06-21 14:13:29 +02:00
Guillaume Chatelet
d395dfa026 Add x86 missing feature detections for ndk_compat (#58) 
One more step towards #47.
 2019-01-22 13:19:42 +01:00
Guillaume Chatelet
439d371594 Adding code. Closes #0. 2018-02-01 10:03:09 +01:00