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Author SHA1 Message Date
Guillaume Chatelet
22a5362e11
[NFC] clang-format codebase (#134) 
* [NFC] clang-format codebase

* revert to 80 char columns at the price of uglier table init

* Specifically disabling clang-format for table initialization
 2020-09-23 09:52:20 +00:00
Mizux
38f2a0274f
ci: Add clang-format check (#132) 
* ci: Add Clang-format check

* ci: Only check file(s) in the commit list
 2020-09-23 09:33:35 +00:00
Guillaume Chatelet
0d47deb9f1
Remove additional dot in README.md 2020-09-23 07:28:19 +00:00
Mizux
a7e0963508
Fix trailing spaces. (#133) 2020-09-23 07:27:23 +00:00
Jeff Hammond
17ffb65117
detect AVX-512 FMA count (#125) 
* add Ice Lake Server and Sapphire Rapids models

The information contained in this commit was obtained from
"Intel® Architecture Instruction Set Extensions and Future Features Programming Reference" document 319433-040 from
https://software.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html

Signed-off-by: Jeff Hammond <jeff.r.hammond@intel.com>

* Tiger Lake; Ice Lake NNP-I; SPR string

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* second FMA features - incomplete and wrong

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* oops: use T/F not 2/1

Signed-off-by: Jeff Hammond <jeff.r.hammond@intel.com>

* implement SKX lookup

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* add Intel copyright

* cleanup AVX512 second FMA code

1) remove debug stuff
2) remove ICX - will add details when available

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* fix CPX detection

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* remove elses

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* remove curly braces from single-line conditional bodies

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* apply clang-format

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

Fixes #120
v0.5.0 		2020-09-22 07:29:46 +00:00
Guillaume Chatelet
76dafc7e3b
[NFC] Remove unused max_cpuid_leaf variable (#131) 2020-09-21 14:54:13 +02:00
Mizux
91f525c74d
Fix ndk-compat include directory (Fix #106) (#130) 2020-09-21 11:42:21 +00:00
Guillaume Chatelet
c186ec5307 [doc] link quickstart within the sample code section 2020-09-21 10:05:16 +00:00
Mizux
4efc837a92
Bump version 0.1.0 -> 0.5.0 (Fix #118) (#129) 2020-09-21 09:59:55 +00:00
Guillaume Chatelet
68fa870479 [Doc] Add C++ namespace to docs 
Fixes #117
 2020-09-21 09:57:09 +00:00
Guillaume Chatelet
3dc868037a Add quickstart to documentation 2020-09-21 09:46:12 +00:00
Jeff Hammond
33bd72c1bc
detect future Intel AVX/AMX features (#124) 
* add Ice Lake Server and Sapphire Rapids models

The information contained in this commit was obtained from
"Intel® Architecture Instruction Set Extensions and Future Features Programming Reference" document 319433-040 from
https://software.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html

Signed-off-by: Jeff Hammond <jeff.r.hammond@intel.com>

* Tiger Lake; Ice Lake NNP-I; SPR string

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* add AVX512_BF16 and AVX512_VP2INTERSECT detection

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* correction for KNM features: s/4VBMI2/4FMAPS/g

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* add AMX/TMUL bits from 319433-040

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* add Intel copyright

Fixes #128
 2020-09-21 07:56:26 +00:00
Jeff Hammond
e698327713
add future Intel microarchitectures (#123) 
* add Ice Lake Server and Sapphire Rapids models

The information contained in this commit was obtained from
"Intel® Architecture Instruction Set Extensions and Future Features Programming Reference" document 319433-040 from
https://software.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html

Signed-off-by: Jeff Hammond <jeff.r.hammond@intel.com>

* Tiger Lake; Ice Lake NNP-I; SPR string

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* add Intel copyright

Fix #127
 2020-09-21 07:54:58 +00:00
Tamas Zsoldos
73d10ad25b
Update features for AArch64 to Linux 5.8 (#122) 
This adds the following features: dcpodp, sve2, sveaes, svepmull,
svebitperm, svesha3, svesm4, flagm2, frint, svei8mm, svef32mm,
svef64mm, svebf16, i8mm, bf16, dgh and rng.

With these, all features used by Linux 5.8 on AArch64 is supported.

Fixes #126
 2020-09-21 07:50:38 +00:00
Henry Lee
9e03e13ae7
Add more test cases for the string view (#119) 2020-09-21 07:39:58 +00:00
Corentin Le Molgat
339bfd32be Add OsSupport structure 2020-03-12 10:58:41 +00:00
Corentin Le Molgat
bee48b4a19 Update .gitignore 
add `build` directory since usually CMake users use
`cmake -S. -Bbuild -DENABLE_TESTING=ON`
 2020-03-12 10:58:41 +00:00
Corentin Le Molgat
404e462cd4 Move AMD extra flags to its own function 2020-03-12 10:58:41 +00:00
gadoofou87
3262a55118 Support x86 FMA4 and SSE4A features 2020-03-12 10:58:41 +00:00
Nikita Karpey
eb168a2da2
Fix shared build (#113) 
* Fix PIC property in util library.
* Force PIC when building shared lib on unix.
* Enable CMP0077 for better option handling.
 2020-03-11 21:54:42 +01:00
Corentin Le Molgat
a83f9d88cd Update gitignore 2020-03-11 20:50:29 +00:00
Corentin Le Molgat
c8e6725f27 Fix travis ci 2020-03-11 20:50:29 +00:00
Nikita Karpey
ba81cb3da9
CMake: Enable CXX compiler for tests only (#110) 
CMake: Enable CXX compiler for tests only

Co-authored-by: Mizux <mizux.dev@gmail.com>
 2020-03-11 14:40:23 +01:00
Mizux
b5c271c537
CMake: Add missing alias for cpu_feature (#107) 
For customers using add_subdirectory() approach

related to #106
 2020-02-06 09:42:20 +01:00
Guillaume Chatelet
5d55aa1efe
Add cache_info data to X86 for list_cpu_features (#105) 
* Add cache_info data to X86 for list_cpu_features
 2020-01-29 15:02:48 +01:00
Guillaume Chatelet
e50d7db3b0 [NFC] Use Designated Initializers 2020-01-29 11:31:10 +01:00
Corentin Le Molgat
ec6354f0f4 Fix case in CPU_FEATURES_COMPILED_X86_AVX2 (Fix #102) 2020-01-29 11:00:11 +01:00
Guillaume Chatelet
a6d219bed7 Fixes #102 - wrong macros 2020-01-29 11:00:11 +01:00
Moxeja
24b8a1de17 Add INTEL_WHL and INTEL_ICL to uarch get name function 2020-01-07 10:18:04 +01:00
Patrick Siegl
3d71a964f5 Use a getter function to avoid manual work for future to-be-added cpu features 2020-01-06 16:24:10 +01:00
Moxeja
73a121b1ae Differentiate between different Lake uarch 2020-01-06 16:23:29 +01:00
Guillaume Chatelet
96552a8ed5 Fix #96 - no member named 'vfpv' in 'ArmFeatures' 2019-11-26 11:05:19 +01:00
Guillaume Chatelet
8a6fd87074 [NFC] Fixed signed shift 
signed shift result (0x80000000) sets the sign bit of the shift expression's type ('int') and becomes negative
 2019-11-13 14:39:06 +01:00
Guillaume Chatelet
77092c6d96
Update LICENSE 
Adding BSD-2-Clauses for `ndk_compat` folder
 2019-11-13 14:36:43 +01:00
Guillaume Chatelet
99d2363c62 [NFC] fix various errors 2019-11-13 11:22:31 +01:00
Guillaume Chatelet
be306b7b15 [NFC] fix unused and shadowing variables 2019-11-13 11:15:40 +01:00
Guillaume Chatelet
3d07d083f2
Merge pull request #95 from gchatelet/master 
Address comments in https://github.com/google/cpu_features/pull/94
 2019-11-12 17:17:59 +01:00
Guillaume Chatelet
9d2de7fb5c Making sure global variable is aligned without using attributes 2019-11-12 17:12:44 +01:00
Guillaume Chatelet
7298eda2ff Making sure global variable is 8B aligned as well 2019-11-12 16:53:04 +01:00
Guillaume Chatelet
0f2f60ab00 Address comments in https://github.com/google/cpu_features/pull/94 2019-11-12 16:26:00 +01:00
Guillaume Chatelet
effc915fcc
Merge pull request #94 from gchatelet/master 
[NFC] Use a tree structure in list_cpu_features
 2019-11-12 14:19:51 +01:00
Guillaume Chatelet
64b1b9090f [NFC] Use a tree structure in list_cpu_features 
This is in preparation to include cache hierarchy in the dumped data.
 2019-11-12 14:00:19 +01:00
Guillaume Chatelet
b5b706cd24
Merge pull request #93 from tamaszarm/aarch64 
Update features for AArch64.
 2019-10-14 15:04:06 +02:00
Tamas Zsoldos
d835b4958c Update features for AArch64. 
Add all missing features up to Linux v5.0.

Features added: evtstrm, atomics, fphp, asimdhp, cpuid, asimdrdm,
jscvt, fcma, lrcpc, dcpop, sha3, sm3, sm4, asimddp, sha512, sve,
asimdfhm, dit, uscat, ilrcpc, flagm, ssbs, sb, paca, pacg.
 2019-10-11 11:02:00 +02:00
Guillaume Chatelet
b9593c8b39
Merge pull request #90 from fexolm/fix-install 
Fixes #91
v0.4.1 		2019-07-16 13:09:50 +02:00
Artem Alekseev
bd358abe6a Fix cmake install 2019-07-16 13:45:33 +03:00
Guillaume Chatelet
f431a8acfd
Merge pull request #88 from skreuzer/bsd 
Fix builds on BSD.
Fixes #89
 2019-07-16 08:43:39 +02:00
Steven Kreuzer
f832ad2b12 Fix builds on BSD 
Fix the build on BSD by setting PROCESSOR_IS_X86 when CMAKE_SYSTEM_PROCESSOR
matches amd64.

Signed-off-by: Steven Kreuzer <skreuzer@FreeBSD.org>
 2019-07-13 22:33:31 -04:00
Guillaume Chatelet
24d7f78814
Use enum properly to directly access kConfig struct (#83) v0.4.0 2019-07-05 08:47:41 +02:00
Dr.-Ing. Patrick Siegl
22c05ed620 Use enum properly to directly access kConfig struct 2019-07-04 21:25:14 +02:00