cdab59af76
[NFC] Simplify build by removing inl files. ( #139 )
2020-10-13 13:05:04 +02:00
9a8f04b24c
[NFC] Generate separate tables via macro ( #137 )
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This is a non functional change, it allows:
- Getting rid of `unix_features_aggregator`
- Have a single blob describing the features
- Fix wrong mocking of `hwcaps`
Downside: abuse of macros makes the code slightly magical and harder to understand.
It think it's still an improvement over the current situation as there's less repetition and less chances to get something wrong.
2020-10-12 09:50:35 +00:00
3cc8f310d9
[NFC] Update copyright from Google Inc. to Google LLC
2020-10-12 08:55:20 +00:00
c0885fec9b
docs: fix simple typo, intented -> intended ( #138 )
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There is a small typo in src/utils/list_cpu_features.c.
Should read `intended` rather than `intented`.
2020-10-12 07:20:05 +00:00
7f62ff67c8
Excluding deleted files from clang-format Check
2020-10-12 07:18:05 +00:00
e63405f118
Remove need for utsname ( #136 )
2020-10-09 20:40:06 +00:00
4795373db2
Fix SSE detection on non-AVX CPUs ( #135 )
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Fixes #4 . This is based on #115 with a few modifications:
- Removed use of __builtin_cpu_supports since it relies on cpuid and doesn't improve on the current situation,
- Added detection for all of sse, sse2, sse3, ssse3, sse4_1 and sse4_2,
- Added tests for Atom, Nehalem, and P3 processors,
Thx to @gadoofou87 for providing the original PR.
It also removes the need for #92
* Fix SSE detection on non-AVX CPUs
* Fixes typo
* Mock OSX sysctlbyname in tests
* Also update other tests
* FakeCpu is reset between each tests
* Fix conflicting name on Windows
* Disable pre AVX cpu sse detection tests on Windows
* Guard OS specific code with macros
* Fix missing import for tests
* Fix wrong function prototype
* Fix wrong mocking of P3 on Windows
* Completely guard OS specific parts in x86 tests
* Store DWORD instead unsigned long for x86 tests
2020-10-09 15:20:25 +00:00
22a5362e11
[NFC] clang-format codebase ( #134 )
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* [NFC] clang-format codebase
* revert to 80 char columns at the price of uglier table init
* Specifically disabling clang-format for table initialization
2020-09-23 09:52:20 +00:00
38f2a0274f
ci: Add clang-format check ( #132 )
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* ci: Add Clang-format check
* ci: Only check file(s) in the commit list
2020-09-23 09:33:35 +00:00
0d47deb9f1
Remove additional dot in README.md
2020-09-23 07:28:19 +00:00
a7e0963508
Fix trailing spaces. ( #133 )
2020-09-23 07:27:23 +00:00
17ffb65117
detect AVX-512 FMA count ( #125 )
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* add Ice Lake Server and Sapphire Rapids models
The information contained in this commit was obtained from
"Intel® Architecture Instruction Set Extensions and Future Features Programming Reference" document 319433-040 from
https://software.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html
Signed-off-by: Jeff Hammond <jeff.r.hammond@intel.com >
* Tiger Lake; Ice Lake NNP-I; SPR string
Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com >
* second FMA features - incomplete and wrong
Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com >
* oops: use T/F not 2/1
Signed-off-by: Jeff Hammond <jeff.r.hammond@intel.com >
* implement SKX lookup
Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com >
* add Intel copyright
* cleanup AVX512 second FMA code
1) remove debug stuff
2) remove ICX - will add details when available
Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com >
* fix CPX detection
Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com >
* remove elses
Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com >
* remove curly braces from single-line conditional bodies
Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com >
* apply clang-format
Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com >
Fixes #120
2020-09-22 07:29:46 +00:00
76dafc7e3b
[NFC] Remove unused max_cpuid_leaf variable ( #131 )
2020-09-21 14:54:13 +02:00
91f525c74d
Fix ndk-compat include directory ( Fix #106 ) ( #130 )
2020-09-21 11:42:21 +00:00
c186ec5307
[doc] link quickstart within the sample code section
2020-09-21 10:05:16 +00:00
4efc837a92
Bump version 0.1.0 -> 0.5.0 ( Fix #118 ) ( #129 )
2020-09-21 09:59:55 +00:00
68fa870479
[Doc] Add C++ namespace to docs
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Fixes #117
2020-09-21 09:57:09 +00:00
3dc868037a
Add quickstart to documentation
2020-09-21 09:46:12 +00:00
33bd72c1bc
detect future Intel AVX/AMX features ( #124 )
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* add Ice Lake Server and Sapphire Rapids models
The information contained in this commit was obtained from
"Intel® Architecture Instruction Set Extensions and Future Features Programming Reference" document 319433-040 from
https://software.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html
Signed-off-by: Jeff Hammond <jeff.r.hammond@intel.com >
* Tiger Lake; Ice Lake NNP-I; SPR string
Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com >
* add AVX512_BF16 and AVX512_VP2INTERSECT detection
Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com >
* correction for KNM features: s/4VBMI2/4FMAPS/g
Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com >
* add AMX/TMUL bits from 319433-040
Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com >
* add Intel copyright
Fixes #128
2020-09-21 07:56:26 +00:00
e698327713
add future Intel microarchitectures ( #123 )
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* add Ice Lake Server and Sapphire Rapids models
The information contained in this commit was obtained from
"Intel® Architecture Instruction Set Extensions and Future Features Programming Reference" document 319433-040 from
https://software.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html
Signed-off-by: Jeff Hammond <jeff.r.hammond@intel.com >
* Tiger Lake; Ice Lake NNP-I; SPR string
Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com >
* add Intel copyright
Fix #127
2020-09-21 07:54:58 +00:00
73d10ad25b
Update features for AArch64 to Linux 5.8 ( #122 )
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This adds the following features: dcpodp, sve2, sveaes, svepmull,
svebitperm, svesha3, svesm4, flagm2, frint, svei8mm, svef32mm,
svef64mm, svebf16, i8mm, bf16, dgh and rng.
With these, all features used by Linux 5.8 on AArch64 is supported.
Fixes #126
2020-09-21 07:50:38 +00:00
9e03e13ae7
Add more test cases for the string view ( #119 )
2020-09-21 07:39:58 +00:00
339bfd32be
Add OsSupport structure
2020-03-12 10:58:41 +00:00
bee48b4a19
Update .gitignore
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add `build` directory since usually CMake users use
`cmake -S. -Bbuild -DENABLE_TESTING=ON`
2020-03-12 10:58:41 +00:00
404e462cd4
Move AMD extra flags to its own function
2020-03-12 10:58:41 +00:00
3262a55118
Support x86 FMA4 and SSE4A features
2020-03-12 10:58:41 +00:00
eb168a2da2
Fix shared build ( #113 )
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* Fix PIC property in util library.
* Force PIC when building shared lib on unix.
* Enable CMP0077 for better option handling.
2020-03-11 21:54:42 +01:00
a83f9d88cd
Update gitignore
2020-03-11 20:50:29 +00:00
c8e6725f27
Fix travis ci
2020-03-11 20:50:29 +00:00
ba81cb3da9
CMake: Enable CXX compiler for tests only ( #110 )
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CMake: Enable CXX compiler for tests only
Co-authored-by: Mizux <mizux.dev@gmail.com >
2020-03-11 14:40:23 +01:00
b5c271c537
CMake: Add missing alias for cpu_feature ( #107 )
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For customers using add_subdirectory() approach
related to #106
2020-02-06 09:42:20 +01:00
5d55aa1efe
Add cache_info data to X86 for list_cpu_features ( #105 )
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* Add cache_info data to X86 for list_cpu_features
2020-01-29 15:02:48 +01:00
e50d7db3b0
[NFC] Use Designated Initializers
2020-01-29 11:31:10 +01:00
ec6354f0f4
Fix case in CPU_FEATURES_COMPILED_X86_AVX2 ( Fix #102 )
2020-01-29 11:00:11 +01:00
a6d219bed7
Fixes #102 - wrong macros
2020-01-29 11:00:11 +01:00
24b8a1de17
Add INTEL_WHL and INTEL_ICL to uarch get name function
2020-01-07 10:18:04 +01:00
3d71a964f5
Use a getter function to avoid manual work for future to-be-added cpu features
2020-01-06 16:24:10 +01:00
73a121b1ae
Differentiate between different Lake uarch
2020-01-06 16:23:29 +01:00
96552a8ed5
Fix #96 - no member named 'vfpv' in 'ArmFeatures'
2019-11-26 11:05:19 +01:00
8a6fd87074
[NFC] Fixed signed shift
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signed shift result (0x80000000) sets the sign bit of the shift expression's type ('int') and becomes negative
2019-11-13 14:39:06 +01:00
77092c6d96
Update LICENSE
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Adding BSD-2-Clauses for `ndk_compat` folder
2019-11-13 14:36:43 +01:00
99d2363c62
[NFC] fix various errors
2019-11-13 11:22:31 +01:00
be306b7b15
[NFC] fix unused and shadowing variables
2019-11-13 11:15:40 +01:00
3d07d083f2
Merge pull request #95 from gchatelet/master
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Address comments in https://github.com/google/cpu_features/pull/94
2019-11-12 17:17:59 +01:00
9d2de7fb5c
Making sure global variable is aligned without using attributes
2019-11-12 17:12:44 +01:00
7298eda2ff
Making sure global variable is 8B aligned as well
2019-11-12 16:53:04 +01:00
0f2f60ab00
Address comments in https://github.com/google/cpu_features/pull/94
2019-11-12 16:26:00 +01:00
effc915fcc
Merge pull request #94 from gchatelet/master
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[NFC] Use a tree structure in list_cpu_features
2019-11-12 14:19:51 +01:00
64b1b9090f
[NFC] Use a tree structure in list_cpu_features
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This is in preparation to include cache hierarchy in the dumped data.
2019-11-12 14:00:19 +01:00
b5b706cd24
Merge pull request #93 from tamaszarm/aarch64
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Update features for AArch64.
2019-10-14 15:04:06 +02:00
