Fixes#4. This is based on #115 with a few modifications:
- Removed use of __builtin_cpu_supports since it relies on cpuid and doesn't improve on the current situation,
- Added detection for all of sse, sse2, sse3, ssse3, sse4_1 and sse4_2,
- Added tests for Atom, Nehalem, and P3 processors,
Thx to @gadoofou87 for providing the original PR.
It also removes the need for #92
* Fix SSE detection on non-AVX CPUs
* Fixes typo
* Mock OSX sysctlbyname in tests
* Also update other tests
* FakeCpu is reset between each tests
* Fix conflicting name on Windows
* Disable pre AVX cpu sse detection tests on Windows
* Guard OS specific code with macros
* Fix missing import for tests
* Fix wrong function prototype
* Fix wrong mocking of P3 on Windows
* Completely guard OS specific parts in x86 tests
* Store DWORD instead unsigned long for x86 tests
* [NFC] clang-format codebase
* revert to 80 char columns at the price of uglier table init
* Specifically disabling clang-format for table initialization
* add Ice Lake Server and Sapphire Rapids models
The information contained in this commit was obtained from
"Intel® Architecture Instruction Set Extensions and Future Features Programming Reference" document 319433-040 from
https://software.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html
Signed-off-by: Jeff Hammond <jeff.r.hammond@intel.com>
* Tiger Lake; Ice Lake NNP-I; SPR string
Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>
* second FMA features - incomplete and wrong
Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>
* oops: use T/F not 2/1
Signed-off-by: Jeff Hammond <jeff.r.hammond@intel.com>
* implement SKX lookup
Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>
* add Intel copyright
* cleanup AVX512 second FMA code
1) remove debug stuff
2) remove ICX - will add details when available
Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>
* fix CPX detection
Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>
* remove elses
Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>
* remove curly braces from single-line conditional bodies
Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>
* apply clang-format
Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>
Fixes#120
* add Ice Lake Server and Sapphire Rapids models
The information contained in this commit was obtained from
"Intel® Architecture Instruction Set Extensions and Future Features Programming Reference" document 319433-040 from
https://software.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html
Signed-off-by: Jeff Hammond <jeff.r.hammond@intel.com>
* Tiger Lake; Ice Lake NNP-I; SPR string
Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>
* add AVX512_BF16 and AVX512_VP2INTERSECT detection
Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>
* correction for KNM features: s/4VBMI2/4FMAPS/g
Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>
* add AMX/TMUL bits from 319433-040
Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>
* add Intel copyright
Fixes#128
This adds the following features: dcpodp, sve2, sveaes, svepmull,
svebitperm, svesha3, svesm4, flagm2, frint, svei8mm, svef32mm,
svef64mm, svebf16, i8mm, bf16, dgh and rng.
With these, all features used by Linux 5.8 on AArch64 is supported.
Fixes#126
