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73 lines
2.3 KiB
C
73 lines
2.3 KiB
C
// Copyright 2022 Google LLC
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef CPU_FEATURES_INCLUDE_CPUINFO_RISCV_H_
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#define CPU_FEATURES_INCLUDE_CPUINFO_RISCV_H_
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#include "cpu_features_cache_info.h"
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#include "cpu_features_macros.h"
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#if !defined(CPU_FEATURES_ARCH_RISCV)
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#error "Including cpuinfo_riscv.h from a non-riscv target."
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#endif
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CPU_FEATURES_START_CPP_NAMESPACE
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typedef struct {
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// Base
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int RV32I : 1; // Base Integer Instruction Set, 32-bit
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int RV64I : 1; // Base Integer Instruction Set, 64-bit
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// Extension
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int M : 1; // Standard Extension for Integer Multiplication/Division
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int A : 1; // Standard Extension for Atomic Instructions
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int F : 1; // Standard Extension for Single-Precision Floating-Point
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int D : 1; // Standard Extension for Double-Precision Floating-Point
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int Q : 1; // Standard Extension for Quad-Precision Floating-Point
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int C : 1; // Standard Extension for Compressed Instructions
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int V : 1; // Standard Extension for Vector Instructions
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int Zicsr : 1; // Control and Status Register (CSR)
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int Zifencei : 1; // Instruction-Fetch Fence
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} RiscvFeatures;
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typedef struct {
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RiscvFeatures features;
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char uarch[64]; // 0 terminated string
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char vendor[64]; // 0 terminated string
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} RiscvInfo;
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typedef enum {
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RISCV_RV32I,
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RISCV_RV64I,
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RISCV_M,
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RISCV_A,
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RISCV_F,
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RISCV_D,
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RISCV_Q,
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RISCV_C,
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RISCV_V,
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RISCV_Zicsr,
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RISCV_Zifencei,
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RISCV_LAST_,
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} RiscvFeaturesEnum;
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RiscvInfo GetRiscvInfo(void);
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int GetRiscvFeaturesEnumValue(const RiscvFeatures* features,
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RiscvFeaturesEnum value);
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const char* GetRiscvFeaturesEnumName(RiscvFeaturesEnum);
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CPU_FEATURES_END_CPP_NAMESPACE
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#endif // CPU_FEATURES_INCLUDE_CPUINFO_RISCV_H_
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