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Code Issues Releases Wiki Activity

Add RISCV vector extension (#289)

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Co-authored-by: Michael Roe <michael-roe@users.noreply.github.com>
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michael-roe 2023-04-24 14:36:22 +01:00 committed by GitHub
parent 5607a689e0
commit 75ec988188
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4 changed files with 28 additions and 0 deletions
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2
include/cpuinfo_riscv.h
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@ -36,6 +36,7 @@ typedef struct {
int D : 1; // Standard Extension for Double-Precision Floating-Point
int Q : 1; // Standard Extension for Quad-Precision Floating-Point
int C : 1; // Standard Extension for Compressed Instructions
int V : 1; // Standard Extension for Vector Instructions
int Zicsr : 1; // Control and Status Register (CSR)
int Zifencei : 1; // Instruction-Fetch Fence
} RiscvFeatures;
@ -55,6 +56,7 @@ typedef enum {
RISCV_D,
RISCV_Q,
RISCV_C,
RISCV_V,
RISCV_Zicsr,
RISCV_Zifencei,
RISCV_LAST_,

1
include/internal/hwcaps.h
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@ -214,6 +214,7 @@ CPU_FEATURES_START_CPP_NAMESPACE
#define RISCV_HWCAP_D (1UL << ('D' - 'A'))
#define RISCV_HWCAP_Q (1UL << ('Q' - 'A'))
#define RISCV_HWCAP_C (1UL << ('C' - 'A'))
#define RISCV_HWCAP_V (1UL << ('V' - 'A'))
typedef struct {
unsigned long hwcaps;

1
src/impl_riscv_linux.c
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@ -39,6 +39,7 @@
LINE(RISCV_D, D, "d", RISCV_HWCAP_D, 0) \
LINE(RISCV_Q, Q, "q", RISCV_HWCAP_Q, 0) \
LINE(RISCV_C, C, "c", RISCV_HWCAP_C, 0) \
LINE(RISCV_V, V, "v", RISCV_HWCAP_V, 0) \
LINE(RISCV_Zicsr, Zicsr, "_zicsr", 0, 0) \
LINE(RISCV_Zifencei, Zifencei, "_zifencei", 0, 0)
#define INTROSPECTION_PREFIX Riscv

24
test/cpuinfo_riscv_test.cc
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@ -41,6 +41,7 @@ uarch : thead,c906)");
EXPECT_TRUE(info.features.D);
EXPECT_FALSE(info.features.Q);
EXPECT_TRUE(info.features.C);
EXPECT_FALSE(info.features.V);
}
// https://github.com/ThomasKaiser/sbc-bench/blob/284e82b016ec1beeac42a5fcbe556b670f68441a/results/Kendryte-K510-4.17.0.cpuinfo
@ -67,6 +68,7 @@ mmu : sv39");
EXPECT_TRUE(info.features.D);
EXPECT_FALSE(info.features.Q);
EXPECT_TRUE(info.features.C);
EXPECT_FALSE(info.features.V);
}
// https://github.com/ThomasKaiser/sbc-bench/blob/284e82b016ec1beeac42a5fcbe556b670f68441a/results/T-Head-C910-5.10.4.cpuinfo
@ -109,6 +111,7 @@ cpu-vector : 0.7.1");
EXPECT_TRUE(info.features.D);
EXPECT_FALSE(info.features.Q);
EXPECT_TRUE(info.features.C);
EXPECT_FALSE(info.features.V);
}
TEST(CpuinfoRiscvTest, UnknownFromCpuInfo) {
@ -150,6 +153,27 @@ uarch : sifive,bullet0)");
EXPECT_TRUE(info.features.D);
EXPECT_FALSE(info.features.Q);
EXPECT_TRUE(info.features.C);
EXPECT_FALSE(info.features.V);
}
TEST(CpuinfoRiscvTest, QemuCpuInfo) {
ResetHwcaps();
auto& fs = GetEmptyFilesystem();
fs.CreateFile("/proc/cpuinfo", R"(
processor : 0
hart : 0
isa : rv64imafdcvh_zba_zbb_zbc_zbs
mmu : sv48)");
const auto info = GetRiscvInfo();
EXPECT_FALSE(info.features.RV32I);
EXPECT_TRUE(info.features.RV64I);
EXPECT_TRUE(info.features.M);
EXPECT_TRUE(info.features.A);
EXPECT_TRUE(info.features.F);
EXPECT_TRUE(info.features.D);
EXPECT_FALSE(info.features.Q);
EXPECT_TRUE(info.features.C);
EXPECT_TRUE(info.features.V);
}
} // namespace