mirror of
https://github.com/google/cpu_features.git
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d835b4958c
Add all missing features up to Linux v5.0. Features added: evtstrm, atomics, fphp, asimdhp, cpuid, asimdrdm, jscvt, fcma, lrcpc, dcpop, sha3, sm3, sm4, asimddp, sha512, sve, asimdfhm, dit, uscat, ilrcpc, flagm, ssbs, sb, paca, pacg.
121 lines
3.8 KiB
C
121 lines
3.8 KiB
C
// Copyright 2017 Google Inc.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef CPU_FEATURES_INCLUDE_CPUINFO_AARCH64_H_
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#define CPU_FEATURES_INCLUDE_CPUINFO_AARCH64_H_
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#include "cpu_features_macros.h"
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#include "cpu_features_cache_info.h"
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CPU_FEATURES_START_CPP_NAMESPACE
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typedef struct {
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int fp : 1; // Floating-point.
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int asimd : 1; // Advanced SIMD.
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int evtstrm : 1; // Generic timer generated events.
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int aes : 1; // Hardware-accelerated Advanced Encryption Standard.
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int pmull : 1; // Polynomial multiply long.
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int sha1 : 1; // Hardware-accelerated SHA1.
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int sha2 : 1; // Hardware-accelerated SHA2-256.
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int crc32 : 1; // Hardware-accelerated CRC-32.
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int atomics : 1; // Armv8.1 atomic instructions.
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int fphp : 1; // Half-precision floating point support.
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int asimdhp : 1; // Advanced SIMD half-precision support.
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int cpuid : 1; // Access to certain ID registers.
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int asimdrdm : 1; // Rounding Double Multiply Accumulate/Subtract.
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int jscvt : 1; // Support for JavaScript conversion.
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int fcma : 1; // Floating point complex numbers.
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int lrcpc : 1; // Support for weaker release consistency.
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int dcpop : 1; // Data persistence writeback.
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int sha3 : 1; // Hardware-accelerated SHA3.
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int sm3 : 1; // Hardware-accelerated SM3.
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int sm4 : 1; // Hardware-accelerated SM4.
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int asimddp : 1; // Dot product instruction.
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int sha512 : 1; // Hardware-accelerated SHA512.
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int sve : 1; // Scalable Vector Extension.
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int asimdfhm : 1; // Additional half-precision instructions.
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int dit : 1; // Data independent timing.
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int uscat : 1; // Unaligned atomics support.
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int ilrcpc : 1; // Additional support for weaker release consistency.
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int flagm : 1; // Flag manipulation instructions.
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int ssbs : 1; // Speculative Store Bypass Safe PSTATE bit.
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int sb : 1; // Speculation barrier.
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int paca : 1; // Address authentication.
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int pacg : 1; // Generic authentication.
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// Make sure to update Aarch64FeaturesEnum below if you add a field here.
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} Aarch64Features;
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typedef struct {
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Aarch64Features features;
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int implementer;
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int variant;
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int part;
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int revision;
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} Aarch64Info;
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Aarch64Info GetAarch64Info(void);
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////////////////////////////////////////////////////////////////////////////////
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// Introspection functions
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typedef enum {
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AARCH64_FP,
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AARCH64_ASIMD,
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AARCH64_EVTSTRM,
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AARCH64_AES,
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AARCH64_PMULL,
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AARCH64_SHA1,
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AARCH64_SHA2,
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AARCH64_CRC32,
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AARCH64_ATOMICS,
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AARCH64_FPHP,
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AARCH64_ASIMDHP,
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AARCH64_CPUID,
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AARCH64_ASIMDRDM,
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AARCH64_JSCVT,
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AARCH64_FCMA,
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AARCH64_LRCPC,
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AARCH64_DCPOP,
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AARCH64_SHA3,
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AARCH64_SM3,
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AARCH64_SM4,
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AARCH64_ASIMDDP,
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AARCH64_SHA512,
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AARCH64_SVE,
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AARCH64_ASIMDFHM,
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AARCH64_DIT,
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AARCH64_USCAT,
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AARCH64_ILRCPC,
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AARCH64_FLAGM,
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AARCH64_SSBS,
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AARCH64_SB,
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AARCH64_PACA,
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AARCH64_PACG,
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AARCH64_LAST_,
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} Aarch64FeaturesEnum;
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int GetAarch64FeaturesEnumValue(const Aarch64Features* features,
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Aarch64FeaturesEnum value);
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const char* GetAarch64FeaturesEnumName(Aarch64FeaturesEnum);
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CPU_FEATURES_END_CPP_NAMESPACE
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#if !defined(CPU_FEATURES_ARCH_AARCH64)
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#error "Including cpuinfo_aarch64.h from a non-aarch64 target."
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#endif
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#endif // CPU_FEATURES_INCLUDE_CPUINFO_AARCH64_H_
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