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Autodetect ITE IT87* LPC->SPI translation on all boards without the need for a board enable
Move boards which had an IT87* SPI board enable from the board enable list to the OK list. Mark the Gigabyte GA-MA78GPM-DS2H as OK. Change the it87spi forced port parameter to it87spiport=... Fix incorrect indentation in the man page. Tested by Ward Vandewege on both variants of the Gigabyte GA-M57SLI-S4 http://www.flashrom.org/pipermail/flashrom/2010-March/002712.html Tested by 李彥學 (Ian-Xue Li) on the Gigabyte GA-MA78GPM-DS2H http://www.flashrom.org/pipermail/flashrom/2010-March/002723.html Corresponding to flashrom svn r983. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Ward Vandewege <ward@gnu.org>
This commit is contained in:
Carl-Daniel Hailfinger
parent
ed479d2a87
commit
01f3ef4fd1
@ -1378,15 +1378,8 @@ struct board_pciid_enable board_pciid_enables[] = {
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{0x10EC, 0x8139, 0x1695, 0x9001, 0x11C1, 0x5811, 0x1695, 0x9015, NULL, NULL, NULL, "EPoX", "EP-8RDA3+", 0, OK, nvidia_mcp_gpio31_raise},
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{0x8086, 0x7110, 0, 0, 0x8086, 0x7190, 0, 0, NULL, "epox", "ep-bx3", "EPoX", "EP-BX3", 0, OK, board_epox_ep_bx3},
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{0x1106, 0x0686, 0x1106, 0x0686, 0x1106, 0x3058, 0x1458, 0xa000, NULL, NULL, NULL, "GIGABYTE", "GA-7ZM", 512, OK, NULL},
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{0x1039, 0x0761, 0, 0, 0x10EC, 0x8168, 0, 0, NULL, "gigabyte", "2761gxdk", "GIGABYTE", "GA-2761GXDK", 0, OK, it87xx_probe_spi_flash},
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{0x1106, 0x3227, 0x1458, 0x5001, 0x10ec, 0x8139, 0x1458, 0xe000, NULL, NULL, NULL, "GIGABYTE", "GA-7VT600", 0, OK, it8705f_write_enable_2e},
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{0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, NULL, "GIGABYTE", "GA-K8N-SLI", 0, OK, nvidia_mcp_gpio21_raise},
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{0x10DE, 0x0360, 0x1458, 0x0C11, 0x10DE, 0x0369, 0x1458, 0x5001, NULL, "gigabyte", "m57sli", "GIGABYTE", "GA-M57SLI-S4", 0, OK, it87xx_probe_spi_flash},
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{0x10de, 0x03e0, 0, 0, 0x10DE, 0x03D0, 0, 0, NULL, NULL, NULL, "GIGABYTE", "GA-M61P-S3", 0, OK, it87xx_probe_spi_flash},
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{0x1002, 0x7910, 0x1458, 0x5000, 0x1002, 0x438D, 0x1458, 0x5001, NULL, NULL, NULL, "GIGABYTE", "GA-MA69VM-S2", 0, OK, it87xx_probe_spi_flash},
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{0x1002, 0x4398, 0x1458, 0x5004, 0x1002, 0x4391, 0x1458, 0xb000, NULL, NULL, NULL, "GIGABYTE", "GA-MA78G-DS3H", 0, OK, it87xx_probe_spi_flash},
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{0x1002, 0x4398, 0x1458, 0x5004, 0x1002, 0x4391, 0x1458, 0xb002, "^GA-MA78GM-S2H$", NULL, NULL, "GIGABYTE", "GA-MA78GM-S2H", 0, OK, it87xx_probe_spi_flash},
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{0x1002, 0x438d, 0x1458, 0x5001, 0x1002, 0x5956, 0x1002, 0x5956, NULL, NULL, NULL, "GIGABYTE", "GA-MA790FX-DQ6", 0, OK, it87xx_probe_spi_flash},
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{0x1166, 0x0223, 0x103c, 0x320d, 0x102b, 0x0522, 0x103c, 0x31fa, NULL, "hp", "dl145_g3", "HP", "DL145 G3", 0, OK, board_hp_dl145_g3_enable},
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{0x8086, 0x2415, 0x103c, 0x1249, 0x10b7, 0x9200, 0x103c, 0x1246, NULL, NULL, NULL, "HP", "Vectra VL400", 0, OK, board_hp_vl400},
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{0x8086, 0x1a30, 0x103c, 0x1a30, 0x8086, 0x2443, 0x103c, 0x2440, "^VL420$", NULL, NULL, "HP", "VL420 SFF", 0, OK, intel_ich_gpio22_raise},
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@ -1414,7 +1407,6 @@ struct board_pciid_enable board_pciid_enables[] = {
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{0x1106, 0x3123, 0x1106, 0x3123, 0x1106, 0x3059, 0x1106, 0x4161, NULL, NULL, NULL, "Termtek", "TK-3370 (Rev:2.5B)", 0, OK, w836xx_memw_enable_4e},
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{0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, NULL, "VIA", "EPIA M/MII/...", 0, OK, via_vt823x_gpio15_raise},
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{0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, NULL, NULL, NULL, "VIA", "EPIA-N/NL", 0, OK, via_vt823x_gpio9_raise},
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{0x1106, 0x5337, 0x1458, 0xb003, 0x1106, 0x287e, 0x1106, 0x337e, NULL, NULL, NULL, "VIA", "PC3500G", 0, OK, it87xx_probe_spi_flash},
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{ 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL, NULL, 0, NT, NULL}, /* end marker */
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};
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13
flashrom.8
13
flashrom.8
@ -220,6 +220,15 @@ has been written because it is known that writing/erasing without the board
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enable is going to fail. In any case (success or failure), please report to
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the flashrom mailing list, see below.
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.sp
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If your mainboard uses an ITE IT87 series Super I/O for LPC<->SPI flash bus
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translation, flashrom should autodetect that configuration. You can use
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.B "flashrom -p internal:it87spiport=portnum"
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syntax as explained in the
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.B it87spi
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programmer section to use a non-default port for controlling the IT87 series
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Super I/O. In the unlikely case flashrom doesn't detect an active IT87 LPC<->SPI
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bridge, you can try to force recognition by using the it87spi programmer.
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.TP
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.BR "dummy " programmer
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An optional parameter specifies the bus types it
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should support. For that you have to use the
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@ -233,7 +242,7 @@ in any order.
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Example:
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.B "flashrom -p dummy:lpc,fwh"
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.TP
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.BR "nic3com" , " gfxnvidia" , " satasii" and " atahpt " programmers
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.BR "nic3com" , " gfxnvidia" , " satasii " and " atahpt " programmers
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These programmers have an option to specify the PCI address of the card
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your want to use, which must be specified if more than one card supported
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by the selected programmer is installed in your system. The syntax is
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@ -255,7 +264,7 @@ Example:
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An optional parameter sets the I/O base port of the IT87* SPI controller
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interface to the port specified in the parameter instead of using the port
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address set by the BIOS. For that you have to use the
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.B "flashrom -p it87spi:port=portnum"
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.B "flashrom -p it87spi:it87spiport=portnum"
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syntax where
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.B portnum
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is an I/O port number which must be a multiple of 8.
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@ -173,6 +173,9 @@ int internal_init(void)
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"will most likely fail.\n");
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}
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/* Probe for IT87* LPC->SPI translation unconditionally. */
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it87xx_probe_spi_flash(NULL);
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board_flash_enable(lb_vendor, lb_part);
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/* Even if chipset init returns an error code, we don't want to abort.
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25
it87spi.c
25
it87spi.c
@ -106,6 +106,14 @@ static uint16_t find_ite_spi_flash_port(uint16_t port, uint16_t id)
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enter_conf_mode_ite(port);
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/* NOLDN, reg 0x24, mask out lowest bit (suspend) */
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tmp = sio_read(port, 0x24) & 0xFE;
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/* If IT87SPI was not explicitly selected, we want to check
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* quickly if LPC->SPI translation is active.
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*/
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if ((programmer == PROGRAMMER_INTERNAL) && !(tmp & (0x0E))) {
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msg_pdbg("No IT87* serial flash segment enabled.\n");
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exit_conf_mode_ite(port);
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break;
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}
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msg_pdbg("Serial flash segment 0x%08x-0x%08x %sabled\n",
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0xFFFE0000, 0xFFFFFFFF, (tmp & 1 << 1) ? "en" : "dis");
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msg_pdbg("Serial flash segment 0x%08x-0x%08x %sabled\n",
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@ -135,12 +143,17 @@ static uint16_t find_ite_spi_flash_port(uint16_t port, uint16_t id)
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free(programmer_param);
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programmer_param = NULL;
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}
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if (programmer_param && (portpos = strstr(programmer_param, "port="))) {
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portpos += 5;
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flashport = strtol(portpos, (char **)NULL, 0);
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msg_pinfo("Forcing serial flash port 0x%04x\n", flashport);
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sio_write(port, 0x64, (flashport >> 8));
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sio_write(port, 0x65, (flashport & 0xff));
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if (programmer_param) {
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portpos = extract_param(&programmer_param,
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"it87spiport=", ",:");
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if (portpos) {
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flashport = strtol(portpos, (char **)NULL, 0);
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msg_pinfo("Forcing serial flash port 0x%04x\n",
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flashport);
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sio_write(port, 0x64, (flashport >> 8));
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sio_write(port, 0x65, (flashport & 0xff));
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free(portpos);
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}
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}
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exit_conf_mode_ite(port);
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break;
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11
print.c
11
print.c
@ -297,16 +297,22 @@ const struct board_info boards_ok[] = {
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{ "DFI", "Blood-Iron P35 T2RL", },
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{ "Elitegroup", "K7S5A", },
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{ "Elitegroup", "P6VAP-A+", },
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{ "GIGABYTE", "GA-2761GXDK", },
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{ "GIGABYTE", "GA-6BXC", },
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{ "GIGABYTE", "GA-6BXDU", },
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{ "GIGABYTE", "GA-6ZMA", },
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{ "GIGABYTE", "GA-7ZM", },
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{ "GIGABYTE", "GA-EP35-DS3L", },
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{ "GIGABYTE", "GA-EX58-UD4P", },
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{ "GIGABYTE", "GA-M57SLI-S4", },
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{ "GIGABYTE", "GA-M61P-S3", },
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{ "GIGABYTE", "GA-MA69VM-S2", },
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{ "GIGABYTE", "GA-MA78GPM-DS2H", },
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{ "GIGABYTE", "GA-MA790GP-DS4H", },
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{ "GIGABYTE", "GA-MA770T-UD3P", },
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{ "GIGABYTE", "GA-MA78G-DS3H", },
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{ "GIGABYTE", "GA-MA78GM-S2H", },
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{ "GIGABYTE", "GA-MA78GPM-DS2H", },
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{ "GIGABYTE", "GA-MA790FX-DQ6", },
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{ "GIGABYTE", "GA-MA790GP-DS4H", },
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{ "Intel", "EP80759", },
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{ "Jetway", "J7F4K1G5D-PB", },
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{ "MSI", "MS-6153", },
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@ -361,6 +367,7 @@ const struct board_info boards_ok[] = {
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{ "VIA", "EPIA-SP", },
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{ "VIA", "NAB74X0", },
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{ "VIA", "pc2500e", },
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{ "VIA", "PC3500G", },
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{ "VIA", "VB700X", },
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{},
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