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flashchips: Add support for MXIC MX25U25645G

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The MX25U25645G has been tested by ch341a programmer : read, write,
erase and wp.

We have tested --wp-enable, --wp-disable, --wp-list and --wp-range
commands for write-protect feature.

MX25U25645G datasheet is available at the following URL:
https://www.mxic.com.tw/Lists/Datasheet/Attachments/8738/MX25U25645G,%201.8V,%20256Mb,%20v1.4.pdf

Change-Id: I8641f36e1909274629690fc243be46281a21360d
Signed-off-by: DanielZhang <danielzhang@mxic.com.cn>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/82777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
This commit is contained in:
DanielZhang 2024-06-03 16:22:26 +08:00 committed by Anastasia Klimchuk
parent 98cff507ca
commit 04d0259ef1
2 changed files with 57 additions and 1 deletions
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56
flashchips.c
View File

@ -11150,6 +11150,62 @@ const struct flashchip flashchips[] = {
.decode_range = DECODE_RANGE_SPI25,
},
{
.vendor = "Macronix",
.name = "MX25U25645G",
.bustype = BUS_SPI,
.manufacture_id = MACRONIX_ID,
.model_id = MACRONIX_MX25U25635F,
.total_size = 32768,
.page_size = 256,
/* OTP: 1024B total; enter 0xB1, exit 0xC1 */
.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI | FEATURE_4BA | FEATURE_CFGR | FEATURE_SCUR,
.tested = TEST_OK_PREWB,
.probe = PROBE_SPI_RDID,
.probe_timing = TIMING_ZERO,
.block_erasers =
{
{
.eraseblocks = { {4 * 1024, 8192} },
.block_erase = SPI_BLOCK_ERASE_21,
}, {
.eraseblocks = { {4 * 1024, 8192} },
.block_erase = SPI_BLOCK_ERASE_20,
}, {
.eraseblocks = { {32 * 1024, 1024} },
.block_erase = SPI_BLOCK_ERASE_5C,
}, {
.eraseblocks = { {32 * 1024, 1024} },
.block_erase = SPI_BLOCK_ERASE_52,
}, {
.eraseblocks = { {64 * 1024, 512} },
.block_erase = SPI_BLOCK_ERASE_DC,
}, {
.eraseblocks = { {64 * 1024, 512} },
.block_erase = SPI_BLOCK_ERASE_D8,
}, {
.eraseblocks = { {32 * 1024 * 1024, 1} },
.block_erase = SPI_BLOCK_ERASE_60,
}, {
.eraseblocks = { {32 * 1024 * 1024, 1} },
.block_erase = SPI_BLOCK_ERASE_C7,
}
},
.printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP3_SRWD, /* bit6 is quad enable */
.unlock = SPI_DISABLE_BLOCKPROTECT_BP3_SRWD,
.write = SPI_CHIP_WRITE256, /* Multi I/O supported */
.read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */
.voltage = {1700, 2000},
.reg_bits =
{
.srp = {STATUS1, 7, RW},
.bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}},
.tb = {CONFIG, 3, OTP},
.wps = {SECURITY, 7, OTP}, /* This bit is set by WPSEL command */
},
.decode_range = DECODE_RANGE_SPI25,
},
{
.vendor = "Macronix",
.name = "MX25U3235E/F",

2
include/flashchips.h
View File

@ -534,7 +534,7 @@
#define MACRONIX_MX25U3235E 0x2536 /* Same as MX25U6435F */
#define MACRONIX_MX25U6435E 0x2537 /* Same as MX25U6435F */
#define MACRONIX_MX25U12835E 0x2538 /* Same as MX25U12835F */
#define MACRONIX_MX25U25635F 0x2539 /* Same as MX25U25643G */
#define MACRONIX_MX25U25635F 0x2539 /* Same as MX25U25643G, MX25U25645G */
#define MACRONIX_MX25U51245G 0x253a
#define MACRONIX_MX25L3235D 0x5E16 /* MX25L3225D/MX25L3235D/MX25L3237D */
#define MACRONIX_MX25L6495F 0x9517