openwrt/flashrom
1
0
Fork 0
mirror of https://review.coreboot.org/flashrom.git synced 2025-04-27 15:12:36 +02:00
Code Issues Releases Wiki Activity

ichspi: Fix 100 series PCH (Skylake) support

Browse Source 
Pretty subtle missing `else` made flashrom treat Skylake like older
chipsets.

Change-Id: I14bf578964124d4677cb5dfca01c9d1b0d279c9c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reported-by: Youness Alaoui <kakaroto@kakaroto.homelinux.net>
Reviewed-on: https://review.coreboot.org/22832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
(cherry picked from commit 19eb0792b8439198d7ef0077b8f79f275fa39a9d)
Reviewed-on: https://review.coreboot.org/22944
This commit is contained in:
Nico Huber 2017-12-13 00:44:45 +01:00
parent 60210dea9e
commit 078d24ef2f
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
ichspi.c
View File

@ -1715,7 +1715,7 @@ int ich_init_spi(void *spibar, enum ich_chipset ich_gen)
hwseq_data.addr_mask = PCH100_FADDR_FLA; hwseq_data.addr_mask = PCH100_FADDR_FLA;
hwseq_data.only_4k = true; hwseq_data.only_4k = true;
hwseq_data.hsfc_fcycle = PCH100_HSFC_FCYCLE; hwseq_data.hsfc_fcycle = PCH100_HSFC_FCYCLE;
} if (ich_generation == CHIPSET_C620_SERIES_LEWISBURG) { } else if (ich_generation == CHIPSET_C620_SERIES_LEWISBURG) {
num_freg = 12; /* 12 MMIO regs, but 16 regions in FD spec */ num_freg = 12; /* 12 MMIO regs, but 16 regions in FD spec */
num_pr = 6; /* Includes GPR0 */ num_pr = 6; /* Includes GPR0 */
reg_pr0 = PCH100_REG_FPR0; reg_pr0 = PCH100_REG_FPR0;