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ichspi: Add Alder Lake support
Does exactly what it says on the tin. BUG=b:220799648 TEST=```localhost ~ # flashrom --flash-name <snip> Found Programmer flash chip "Opaque flash chip" (32768 kB, Programmer-specific) mapped at physical address 0x0000000000000000. vendor="Programmer" name="Opaque flash chip" flashrom -p internal --ifd -i fd -i bios -r /tmp/filename.rom flashrom unknown on Linux 5.15.22 (x86_64) flashrom is free software, get the source code at https://flashrom.org Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). coreboot table found at 0x768a7000. Found chipset "Intel Alder Lake-N". Enabling flash write... Warning: Setting BIOS Control at 0xdc from 0x8b to 0x89 failed. New value is 0x8b. SPI Configuration is locked down. OK. Found Winbond flash chip "W25Q256JV_M" (32768 kB, Programmer-specific) mapped at physical address 0x0000000000000000. Error accessing W25Q256JV_M, 0x2000000 bytes at 0x00000000fe000000 /dev/mem mmap failed: Resource temporarily unavailable Could not map flash chip W25Q256JV_M at 0x00000000fe000000. Reading ich descriptor... done. Using regions: "bios", "fd". Error accessing W25Q256JV_M, 0x2000000 bytes at 0x00000000fe000000 /dev/mem mmap failed: Resource temporarily unavailable Could not map flash chip W25Q256JV_M at 0x00000000fe000000. Reading flash... done. SUCCESS Also, Reading ich descriptor... Reading 4096 bytes starting at 0x000000. done. Assuming chipset '600 series Alder Point'. Added layout entry 00000000 - 00000fff named fd Added layout entry 00500000 - 01ffffff named bios Added layout entry 00001000 - 004fffff named me ``` Tested on Nivviks/ADL-N and Brya/ADL-P. Change-Id: Ie66cf519df13f3391c41f5016b16a81ef3dfd4bf Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sam McNally <sammc@google.com>
This commit is contained in:
Edward O'Callaghan
Edward O'Callaghan
parent
6289508c5b
commit
11680db4e1
@ -605,6 +605,7 @@ static enum chipbustype enable_flash_ich_report_gcs(
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case CHIPSET_300_SERIES_CANNON_POINT:
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case CHIPSET_400_SERIES_COMET_POINT:
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case CHIPSET_500_SERIES_TIGER_POINT:
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case CHIPSET_600_SERIES_ALDER_POINT:
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case CHIPSET_ELKHART_LAKE:
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case CHIPSET_APOLLO_LAKE:
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case CHIPSET_GEMINI_LAKE:
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@ -709,6 +710,7 @@ static enum chipbustype enable_flash_ich_report_gcs(
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boot_straps = boot_straps_pch8_lp;
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break;
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case CHIPSET_500_SERIES_TIGER_POINT:
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case CHIPSET_600_SERIES_ALDER_POINT:
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boot_straps = boot_straps_pch500;
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break;
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case CHIPSET_APOLLO_LAKE:
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@ -741,6 +743,7 @@ static enum chipbustype enable_flash_ich_report_gcs(
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case CHIPSET_300_SERIES_CANNON_POINT:
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case CHIPSET_400_SERIES_COMET_POINT:
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case CHIPSET_500_SERIES_TIGER_POINT:
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case CHIPSET_600_SERIES_ALDER_POINT:
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case CHIPSET_APOLLO_LAKE:
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case CHIPSET_GEMINI_LAKE:
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case CHIPSET_ELKHART_LAKE:
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@ -994,6 +997,11 @@ static int enable_flash_pch500(struct pci_dev *const dev, const char *const name
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return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_500_SERIES_TIGER_POINT);
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}
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static int enable_flash_pch600(struct pci_dev *const dev, const char *const name)
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{
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return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_600_SERIES_ALDER_POINT);
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}
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static int enable_flash_mcc(struct pci_dev *const dev, const char *const name)
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{
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return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_ELKHART_LAKE);
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@ -2141,6 +2149,8 @@ const struct penable chipset_enables[] = {
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{0x8086, 0x4389, B_S, NT, "Intel", "WM590", enable_flash_pch500},
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{0x8086, 0x438a, B_S, NT, "Intel", "QM580", enable_flash_pch500},
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{0x8086, 0x438b, B_S, DEP, "Intel", "HM570", enable_flash_pch500},
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{0x8086, 0x54a4, B_S, DEP, "Intel", "Alder Lake-N", enable_flash_pch600},
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{0x8086, 0x51a4, B_S, DEP, "Intel", "Alder Lake-P", enable_flash_pch600},
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#endif
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{0},
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};
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@ -46,6 +46,7 @@ ssize_t ich_number_of_regions(const enum ich_chipset cs, const struct ich_desc_c
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case CHIPSET_300_SERIES_CANNON_POINT:
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case CHIPSET_400_SERIES_COMET_POINT:
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case CHIPSET_500_SERIES_TIGER_POINT:
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case CHIPSET_600_SERIES_ALDER_POINT:
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case CHIPSET_ELKHART_LAKE:
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return 16;
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case CHIPSET_100_SERIES_SUNRISE_POINT:
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@ -72,6 +73,7 @@ ssize_t ich_number_of_masters(const enum ich_chipset cs, const struct ich_desc_c
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switch (cs) {
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case CHIPSET_C620_SERIES_LEWISBURG:
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case CHIPSET_APOLLO_LAKE:
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case CHIPSET_600_SERIES_ALDER_POINT:
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case CHIPSET_GEMINI_LAKE:
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case CHIPSET_ELKHART_LAKE:
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if (cont->NM <= MAX_NUM_MASTERS)
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@ -111,7 +113,7 @@ void prettyprint_ich_chipset(enum ich_chipset cs)
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"8 series Lynx Point", "Baytrail", "8 series Lynx Point LP", "8 series Wellsburg",
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"9 series Wildcat Point", "9 series Wildcat Point LP", "100 series Sunrise Point",
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"C620 series Lewisburg", "300 series Cannon Point", "400 series Comet Point",
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"500 series Tiger Point", "Apollo Lake", "Gemini Lake", "Elkhart Lake",
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"500 series Tiger Point", "600 series Alder Point", "Apollo Lake", "Gemini Lake", "Elkhart Lake",
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};
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if (cs < CHIPSET_ICH8 || cs - CHIPSET_ICH8 + 1 >= ARRAY_SIZE(chipset_names))
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cs = 0;
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@ -206,6 +208,7 @@ static const char *pprint_density(enum ich_chipset cs, const struct ich_descript
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case CHIPSET_300_SERIES_CANNON_POINT:
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case CHIPSET_400_SERIES_COMET_POINT:
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case CHIPSET_500_SERIES_TIGER_POINT:
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case CHIPSET_600_SERIES_ALDER_POINT:
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case CHIPSET_APOLLO_LAKE:
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case CHIPSET_GEMINI_LAKE:
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case CHIPSET_ELKHART_LAKE: {
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@ -300,6 +303,7 @@ static const char *pprint_freq(enum ich_chipset cs, uint8_t value)
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case CHIPSET_GEMINI_LAKE:
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return freq_str[2][value];
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case CHIPSET_500_SERIES_TIGER_POINT:
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case CHIPSET_600_SERIES_ALDER_POINT:
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return freq_str[3][value];
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case CHIPSET_ELKHART_LAKE:
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return freq_str[4][value];
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@ -346,6 +350,7 @@ void prettyprint_ich_descriptor_component(enum ich_chipset cs, const struct ich_
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case CHIPSET_300_SERIES_CANNON_POINT:
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case CHIPSET_400_SERIES_COMET_POINT:
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case CHIPSET_500_SERIES_TIGER_POINT:
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case CHIPSET_600_SERIES_ALDER_POINT:
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case CHIPSET_APOLLO_LAKE:
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case CHIPSET_GEMINI_LAKE:
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case CHIPSET_ELKHART_LAKE:
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@ -470,7 +475,8 @@ void prettyprint_ich_descriptor_master(const enum ich_chipset cs, const struct i
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if (cs == CHIPSET_100_SERIES_SUNRISE_POINT ||
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cs == CHIPSET_300_SERIES_CANNON_POINT ||
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cs == CHIPSET_400_SERIES_COMET_POINT ||
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cs == CHIPSET_500_SERIES_TIGER_POINT) {
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cs == CHIPSET_500_SERIES_TIGER_POINT ||
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cs == CHIPSET_600_SERIES_ALDER_POINT) {
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const char *const master_names[] = {
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"BIOS", "ME", "GbE", "unknown", "EC",
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};
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@ -1031,6 +1037,8 @@ static enum ich_chipset guess_ich_chipset_from_content(const struct ich_desc_con
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return CHIPSET_300_SERIES_CANNON_POINT;
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if (content->CSSL == 0x11)
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return CHIPSET_500_SERIES_TIGER_POINT;
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if (content->CSSL == 0x14)
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return CHIPSET_600_SERIES_ALDER_POINT;
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if (content->CSSL == 0x03)
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return CHIPSET_ELKHART_LAKE;
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msg_pwarn("Unknown flash descriptor, assuming 500 series compatibility.\n");
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@ -1054,6 +1062,7 @@ static enum ich_chipset guess_ich_chipset(const struct ich_desc_content *const c
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case CHIPSET_300_SERIES_CANNON_POINT:
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case CHIPSET_400_SERIES_COMET_POINT:
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case CHIPSET_500_SERIES_TIGER_POINT:
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case CHIPSET_600_SERIES_ALDER_POINT:
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case CHIPSET_GEMINI_LAKE:
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case CHIPSET_ELKHART_LAKE:
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/* `freq_read` was repurposed, so can't check on it any more. */
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@ -1210,6 +1219,7 @@ int getFCBA_component_density(enum ich_chipset cs, const struct ich_descriptors
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case CHIPSET_300_SERIES_CANNON_POINT:
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case CHIPSET_400_SERIES_COMET_POINT:
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case CHIPSET_500_SERIES_TIGER_POINT:
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case CHIPSET_600_SERIES_ALDER_POINT:
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case CHIPSET_APOLLO_LAKE:
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case CHIPSET_GEMINI_LAKE:
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case CHIPSET_ELKHART_LAKE:
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@ -1249,6 +1259,7 @@ static uint32_t read_descriptor_reg(enum ich_chipset cs, uint8_t section, uint16
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case CHIPSET_300_SERIES_CANNON_POINT:
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case CHIPSET_400_SERIES_COMET_POINT:
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case CHIPSET_500_SERIES_TIGER_POINT:
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case CHIPSET_600_SERIES_ALDER_POINT:
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case CHIPSET_APOLLO_LAKE:
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case CHIPSET_GEMINI_LAKE:
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case CHIPSET_ELKHART_LAKE:
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8
ichspi.c
8
ichspi.c
@ -1781,6 +1781,7 @@ static void init_chipset_properties(struct swseq_data *swseq, struct hwseq_data
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case CHIPSET_300_SERIES_CANNON_POINT:
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case CHIPSET_400_SERIES_COMET_POINT:
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case CHIPSET_500_SERIES_TIGER_POINT:
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case CHIPSET_600_SERIES_ALDER_POINT:
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case CHIPSET_APOLLO_LAKE:
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case CHIPSET_GEMINI_LAKE:
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case CHIPSET_ELKHART_LAKE:
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@ -1817,6 +1818,7 @@ static void init_chipset_properties(struct swseq_data *swseq, struct hwseq_data
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case CHIPSET_300_SERIES_CANNON_POINT:
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case CHIPSET_400_SERIES_COMET_POINT:
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case CHIPSET_500_SERIES_TIGER_POINT:
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case CHIPSET_600_SERIES_ALDER_POINT:
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case CHIPSET_APOLLO_LAKE:
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case CHIPSET_GEMINI_LAKE:
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case CHIPSET_ELKHART_LAKE:
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@ -1875,6 +1877,7 @@ static int init_ich_default(void *spibar, enum ich_chipset ich_gen)
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case CHIPSET_300_SERIES_CANNON_POINT:
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case CHIPSET_400_SERIES_COMET_POINT:
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case CHIPSET_500_SERIES_TIGER_POINT:
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case CHIPSET_600_SERIES_ALDER_POINT:
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case CHIPSET_APOLLO_LAKE:
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case CHIPSET_GEMINI_LAKE:
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case CHIPSET_ELKHART_LAKE:
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@ -1952,6 +1955,7 @@ static int init_ich_default(void *spibar, enum ich_chipset ich_gen)
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case CHIPSET_300_SERIES_CANNON_POINT:
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case CHIPSET_400_SERIES_COMET_POINT:
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case CHIPSET_500_SERIES_TIGER_POINT:
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case CHIPSET_600_SERIES_ALDER_POINT:
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case CHIPSET_APOLLO_LAKE:
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case CHIPSET_GEMINI_LAKE:
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case CHIPSET_BAYTRAIL:
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@ -1988,6 +1992,7 @@ static int init_ich_default(void *spibar, enum ich_chipset ich_gen)
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case CHIPSET_300_SERIES_CANNON_POINT:
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case CHIPSET_400_SERIES_COMET_POINT:
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case CHIPSET_500_SERIES_TIGER_POINT:
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case CHIPSET_600_SERIES_ALDER_POINT:
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case CHIPSET_APOLLO_LAKE:
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case CHIPSET_GEMINI_LAKE:
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case CHIPSET_ELKHART_LAKE:
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@ -2022,7 +2027,8 @@ static int init_ich_default(void *spibar, enum ich_chipset ich_gen)
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(ich_gen == CHIPSET_100_SERIES_SUNRISE_POINT ||
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ich_gen == CHIPSET_300_SERIES_CANNON_POINT ||
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ich_gen == CHIPSET_400_SERIES_COMET_POINT ||
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ich_gen == CHIPSET_500_SERIES_TIGER_POINT)) {
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ich_gen == CHIPSET_500_SERIES_TIGER_POINT ||
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ich_gen == CHIPSET_600_SERIES_ALDER_POINT)) {
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msg_pdbg("Enabling hardware sequencing by default for 100+ series PCH.\n");
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ich_spi_mode = ich_hwseq;
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}
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@ -353,6 +353,7 @@ enum ich_chipset {
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CHIPSET_300_SERIES_CANNON_POINT,
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CHIPSET_400_SERIES_COMET_POINT,
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CHIPSET_500_SERIES_TIGER_POINT,
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CHIPSET_600_SERIES_ALDER_POINT,
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CHIPSET_APOLLO_LAKE,
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CHIPSET_GEMINI_LAKE,
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CHIPSET_ELKHART_LAKE,
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@ -137,6 +137,7 @@ static void usage(char *argv[], const char *error)
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"\t- \"300\" or \"cannon\" for Intel's 300 series chipsets.\n"
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"\t- \"400\" or \"comet\" for Intel's 400 series chipsets.\n"
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"\t- \"500\" or \"tiger\" for Intel's 500 series chipsets.\n"
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"\t- \"600\" or \"alder\" for Intel's 600 series chipsets.\n"
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"If '-d' is specified some regions such as the BIOS image as seen by the CPU or\n"
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"the GbE blob that is required to initialize the GbE are also dumped to files.\n",
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argv[0], argv[0]);
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@ -234,6 +235,8 @@ int main(int argc, char *argv[])
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else if ((strcmp(csn, "500") == 0) ||
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(strcmp(csn, "tiger") == 0))
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cs = CHIPSET_500_SERIES_TIGER_POINT;
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else if (strcmp(csn, "600") == 0)
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cs = CHIPSET_600_SERIES_ALDER_POINT;
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else if (strcmp(csn, "apollo") == 0)
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cs = CHIPSET_APOLLO_LAKE;
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else if (strcmp(csn, "gemini") == 0)
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