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ichspi: Increase timeout to 60s for atomic operations

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Corresponding to flashrom svn r1290.

Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
This commit is contained in:
Michael Karcher 2011-04-29 22:11:36 +00:00
parent bfecef6986
commit 136125af19
1 changed files with 18 additions and 4 deletions
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22
ichspi.c
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@ -572,7 +572,14 @@ static int ich7_run_opcode(OPCODE op, uint32_t offset,
} }
temp16 |= ((uint16_t) (opcode_index & 0x07)) << 4; temp16 |= ((uint16_t) (opcode_index & 0x07)) << 4;
/* Handle Atomic */ timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */
/* Handle Atomic. Atomic commands include three steps:
- sending the preop (mainly EWSR or WREN)
- sending the main command
- waiting for the busy bit (WIP) to be cleared
This means the timeout must be sufficient for chip erase
of slow high-capacity chips.
*/
switch (op.atomic) { switch (op.atomic) {
case 2: case 2:
/* Select second preop. */ /* Select second preop. */
@ -581,6 +588,7 @@ static int ich7_run_opcode(OPCODE op, uint32_t offset,
case 1: case 1:
/* Atomic command (preop+op) */ /* Atomic command (preop+op) */
temp16 |= SPIC_ACS; temp16 |= SPIC_ACS;
timeout = 100 * 1000 * 60; /* 60 seconds */
break; break;
} }
@ -591,7 +599,6 @@ static int ich7_run_opcode(OPCODE op, uint32_t offset,
REGWRITE16(ICH7_REG_SPIC, temp16); REGWRITE16(ICH7_REG_SPIC, temp16);
/* Wait for Cycle Done Status or Flash Cycle Error. */ /* Wait for Cycle Done Status or Flash Cycle Error. */
timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */
while (((REGREAD16(ICH7_REG_SPIS) & (SPIS_CDS | SPIS_FCERR)) == 0) && while (((REGREAD16(ICH7_REG_SPIS) & (SPIS_CDS | SPIS_FCERR)) == 0) &&
--timeout) { --timeout) {
programmer_delay(10); programmer_delay(10);
@ -711,7 +718,14 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset,
} }
temp32 |= ((uint32_t) (opcode_index & 0x07)) << (8 + 4); temp32 |= ((uint32_t) (opcode_index & 0x07)) << (8 + 4);
/* Handle Atomic */ timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */
/* Handle Atomic. Atomic commands include three steps:
- sending the preop (mainly EWSR or WREN)
- sending the main command
- waiting for the busy bit (WIP) to be cleared
This means the timeout must be sufficient for chip erase
of slow high-capacity chips.
*/
switch (op.atomic) { switch (op.atomic) {
case 2: case 2:
/* Select second preop. */ /* Select second preop. */
@ -720,6 +734,7 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset,
case 1: case 1:
/* Atomic command (preop+op) */ /* Atomic command (preop+op) */
temp32 |= SSFC_ACS; temp32 |= SSFC_ACS;
timeout = 100 * 1000 * 60; /* 60 seconds */
break; break;
} }
@ -730,7 +745,6 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset,
REGWRITE32(ICH9_REG_SSFS, temp32); REGWRITE32(ICH9_REG_SSFS, temp32);
/* Wait for Cycle Done Status or Flash Cycle Error. */ /* Wait for Cycle Done Status or Flash Cycle Error. */
timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */
while (((REGREAD32(ICH9_REG_SSFS) & (SSFS_CDS | SSFS_FCERR)) == 0) && while (((REGREAD32(ICH9_REG_SSFS) & (SSFS_CDS | SSFS_FCERR)) == 0) &&
--timeout) { --timeout) {
programmer_delay(10); programmer_delay(10);