mirror of
https://review.coreboot.org/flashrom.git
synced 2025-04-27 15:12:36 +02:00
Add support for more than one Super I/O or EC per machine
Flashrom currently only supports exactly one Super I/O or Embedded Controller, and this means quite a few notebooks and a small subset of desktop/server boards cannot be handled reliably and easily. Allow detection and initialization of up to 3 Super I/O and/or EC chips. WARNING! If a Super I/O or EC responds on multiple ports (0x2e and 0x4e), the code will do the wrong thing (namely, initialize the hardware twice). I have no idea if we should handle such situations, and whether we should ignore the second chip with identical ID or not. Initializing the hardware twice for the IT87* family is _not_ a problem, but I don't know how well IT85* can handle it (and whether IT85* would listen at more than one port anyway). Corresponding to flashrom svn r1289. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Thanks to Thomas Schneider for testing on a board with ITE IT87* SPI. Test report (success) is here: http://paste.flashrom.org/view.php?id=379 Thanks to David Hendricks for testing on a Google Cr-48 laptop with ITE IT85* EC SPI. Test report (success) is here: http://www.flashrom.org/pipermail/flashrom/2011-April/006275.html Acked-by: David Hendricks <dhendrix@google.com>
This commit is contained in:
Carl-Daniel Hailfinger
parent
880e867ae8
commit
bfecef6986
@ -493,7 +493,6 @@ int it8705f_write_enable(uint8_t port)
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}
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} else {
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msg_pdbg("No IT8705F flash segment enabled.\n");
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/* Not sure if this is an error or not. */
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ret = 0;
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}
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exit_conf_mode_ite(port);
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21
flashrom.c
21
flashrom.c
@ -295,27 +295,6 @@ const struct programmer_entry programmer_table[] = {
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},
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#endif
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#if CONFIG_INTERNAL == 1
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#if defined(__i386__) || defined(__x86_64__)
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{
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.name = "it87spi",
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.init = it87spi_init,
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.shutdown = noop_shutdown,
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.map_flash_region = fallback_map,
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.unmap_flash_region = fallback_unmap,
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.chip_readb = noop_chip_readb,
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.chip_readw = fallback_chip_readw,
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.chip_readl = fallback_chip_readl,
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.chip_readn = fallback_chip_readn,
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.chip_writeb = noop_chip_writeb,
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.chip_writew = fallback_chip_writew,
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.chip_writel = fallback_chip_writel,
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.chip_writen = fallback_chip_writen,
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.delay = internal_delay,
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},
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#endif
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#endif
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#if CONFIG_FT2232_SPI == 1
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{
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.name = "ft2232_spi",
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18
internal.c
18
internal.c
@ -99,17 +99,29 @@ int force_boardenable = 0;
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int force_boardmismatch = 0;
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#if defined(__i386__) || defined(__x86_64__)
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struct superio superio = {};
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void probe_superio(void)
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{
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superio = probe_superio_ite();
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probe_superio_ite();
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#if 0
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/* Winbond Super I/O code is not yet available. */
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if (superio.vendor == SUPERIO_VENDOR_NONE)
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superio = probe_superio_winbond();
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#endif
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}
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int superio_count = 0;
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#define SUPERIO_MAX_COUNT 3
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struct superio superios[SUPERIO_MAX_COUNT];
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int register_superio(struct superio s)
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{
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if (superio_count == SUPERIO_MAX_COUNT)
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return 1;
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superios[superio_count++] = s;
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return 0;
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}
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#endif
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int is_laptop = 0;
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76
it85spi.c
76
it85spi.c
@ -47,9 +47,6 @@
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/* Constants for Logical Device registers */
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#define LDNSEL 0x07
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#define CHIP_ID_BYTE1_REG 0x20
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#define CHIP_ID_BYTE2_REG 0x21
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#define CHIP_CHIP_VER_REG 0x22
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/* These are standard Super I/O 16-bit base address registers */
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#define SHM_IO_BAR0 0x60 /* big-endian, this is high bits */
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@ -86,44 +83,6 @@ unsigned int shm_io_base;
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unsigned char *ce_high, *ce_low;
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static int it85xx_scratch_rom_reenter = 0;
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uint16_t probe_id_ite85(uint16_t port)
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{
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uint16_t id;
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id = sio_read(port, CHIP_ID_BYTE1_REG) << 8 |
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sio_read(port, CHIP_ID_BYTE2_REG);
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return id;
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}
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struct superio probe_superio_ite85xx(void)
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{
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struct superio ret = {};
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uint16_t ite_ports[] = {ITE_SUPERIO_PORT1, ITE_SUPERIO_PORT2, 0};
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uint16_t *i = ite_ports;
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ret.vendor = SUPERIO_VENDOR_ITE;
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for (; *i; i++) {
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ret.port = *i;
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ret.model = probe_id_ite85(ret.port);
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switch (ret.model >> 8) {
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case 0x85:
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msg_pdbg("Found EC: ITE85xx (Vendor:0x%02x,ID:0x%02x,"
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"Rev:0x%02x) on sio_port:0x%x.\n",
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ret.model >> 8, ret.model & 0xff,
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sio_read(ret.port, CHIP_CHIP_VER_REG),
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ret.port);
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return ret;
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}
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}
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/* No good ID found. */
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ret.vendor = SUPERIO_VENDOR_NONE;
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ret.port = 0;
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ret.model = 0;
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return ret;
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}
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/* This function will poll the keyboard status register until either
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* an expected value shows up, or
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* timeout reaches.
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@ -267,20 +226,18 @@ void it85xx_exit_scratch_rom()
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#endif
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}
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int it85xx_spi_common_init(void)
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static int it85xx_spi_common_init(struct superio s)
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{
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chipaddr base;
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msg_pdbg("%s():%d superio.vendor=0x%02x\n", __func__, __LINE__,
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superio.vendor);
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if (superio.vendor != SUPERIO_VENDOR_ITE)
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return 1;
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s.vendor);
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#ifdef LPC_IO
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/* Get LPCPNP of SHM. That's big-endian */
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sio_write(superio.port, LDNSEL, 0x0F); /* Set LDN to SHM (0x0F) */
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shm_io_base = (sio_read(superio.port, SHM_IO_BAR0) << 8) +
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sio_read(superio.port, SHM_IO_BAR1);
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sio_write(s.port, LDNSEL, 0x0F); /* Set LDN to SHM (0x0F) */
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shm_io_base = (sio_read(s.port, SHM_IO_BAR0) << 8) +
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sio_read(s.port, SHM_IO_BAR1);
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msg_pdbg("%s():%d shm_io_base=0x%04x\n", __func__, __LINE__,
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shm_io_base);
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@ -311,25 +268,7 @@ int it85xx_spi_common_init(void)
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return 0;
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}
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/* Called by programmer_entry .init */
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int it85xx_spi_init(void)
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{
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int ret;
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get_io_perms();
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/* Probe for the Super I/O chip and fill global struct superio. */
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probe_superio();
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ret = it85xx_spi_common_init();
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if (!ret) {
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buses_supported = CHIP_BUSTYPE_SPI;
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} else {
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buses_supported = CHIP_BUSTYPE_NONE;
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}
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return ret;
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}
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/* Called by internal_init() */
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int it85xx_probe_spi_flash(void)
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int it85xx_spi_init(struct superio s)
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{
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int ret;
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@ -337,13 +276,14 @@ int it85xx_probe_spi_flash(void)
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msg_pdbg("%s():%d buses not support FWH\n", __func__, __LINE__);
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return 1;
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}
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ret = it85xx_spi_common_init();
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ret = it85xx_spi_common_init(s);
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msg_pdbg("FWH: %s():%d ret=%d\n", __func__, __LINE__, ret);
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if (!ret) {
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msg_pdbg("%s():%d buses_supported=0x%x\n", __func__, __LINE__,
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buses_supported);
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if (buses_supported & CHIP_BUSTYPE_FWH)
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msg_pdbg("Overriding chipset SPI with IT85 FWH|SPI.\n");
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/* Really leave FWH enabled? */
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buses_supported |= CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI;
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}
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return ret;
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117
it87spi.c
117
it87spi.c
@ -42,6 +42,7 @@ static int fast_spi = 1;
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/* Helper functions for most recent ITE IT87xx Super I/O chips */
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#define CHIP_ID_BYTE1_REG 0x20
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#define CHIP_ID_BYTE2_REG 0x21
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#define CHIP_VER_REG 0x22
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void enter_conf_mode_ite(uint16_t port)
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{
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OUTB(0x87, port);
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@ -70,31 +71,37 @@ uint16_t probe_id_ite(uint16_t port)
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return id;
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}
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struct superio probe_superio_ite(void)
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void probe_superio_ite(void)
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{
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struct superio ret = {};
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struct superio s = {};
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uint16_t ite_ports[] = {ITE_SUPERIO_PORT1, ITE_SUPERIO_PORT2, 0};
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uint16_t *i = ite_ports;
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ret.vendor = SUPERIO_VENDOR_ITE;
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s.vendor = SUPERIO_VENDOR_ITE;
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for (; *i; i++) {
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ret.port = *i;
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ret.model = probe_id_ite(ret.port);
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switch (ret.model >> 8) {
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s.port = *i;
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s.model = probe_id_ite(s.port);
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switch (s.model >> 8) {
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case 0x82:
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case 0x86:
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case 0x87:
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msg_pinfo("Found ITE Super I/O, ID 0x%04hx.\n",
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ret.model);
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return ret;
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/* FIXME: Print revision for all models? */
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msg_pdbg("Found ITE Super I/O, ID 0x%04hx on port "
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"0x%x\n", s.model, s.port);
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register_superio(s);
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break;
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case 0x85:
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msg_pdbg("Found ITE EC, ID 0x%04hx,"
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"Rev 0x%02x on port 0x%x.\n",
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s.model,
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sio_read(s.port, CHIP_VER_REG),
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s.port);
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register_superio(s);
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break;
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}
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}
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/* No good ID found. */
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ret.vendor = SUPERIO_VENDOR_NONE;
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ret.port = 0;
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ret.model = 0;
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return ret;
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return;
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}
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static uint16_t it87spi_probe(uint16_t port)
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@ -113,7 +120,7 @@ static uint16_t it87spi_probe(uint16_t port)
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msg_pdbg("No IT87* serial flash segment enabled.\n");
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exit_conf_mode_ite(port);
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/* Nothing to do. */
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return 1;
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return 0;
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}
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msg_pdbg("Serial flash segment 0x%08x-0x%08x %sabled\n",
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0xFFFE0000, 0xFFFFFFFF, (tmp & 1 << 1) ? "en" : "dis");
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@ -159,10 +166,7 @@ static uint16_t it87spi_probe(uint16_t port)
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"port specified.\nPort must be a multiple of "
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"0x8 and lie between 0x100 and 0xff8.\n");
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free(portpos);
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/* FIXME: Return failure here once it87spi_common_init()
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* can handle the return value sanely.
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*/
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exit(1);
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return 1;
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} else {
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flashport = (uint16_t)forced_flashport;
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msg_pinfo("Forcing serial flash port 0x%04x\n",
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@ -177,44 +181,46 @@ static uint16_t it87spi_probe(uint16_t port)
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if (buses_supported & CHIP_BUSTYPE_SPI)
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msg_pdbg("Overriding chipset SPI with IT87 SPI.\n");
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spi_controller = SPI_CONTROLLER_IT87XX;
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/* FIXME: Add the SPI bus or replace the other buses with it? */
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buses_supported |= CHIP_BUSTYPE_SPI;
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return 0;
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}
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int init_superio_ite(void)
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{
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if (superio.vendor != SUPERIO_VENDOR_ITE)
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return 1;
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int i;
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int ret = 0;
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switch (superio.model) {
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case 0x8705:
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return it8705f_write_enable(superio.port);
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break;
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case 0x8716:
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case 0x8718:
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case 0x8720:
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return it87spi_probe(superio.port);
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break;
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default:
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msg_pdbg("Super I/O ID 0x%04hx is not on the list of flash "
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"capable controllers.\n", superio.model);
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}
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return 1;
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}
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for (i = 0; i < superio_count; i++) {
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if (superios[i].vendor != SUPERIO_VENDOR_ITE)
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continue;
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int it87spi_init(void)
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{
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int ret;
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get_io_perms();
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/* Probe for the Super I/O chip and fill global struct superio. */
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probe_superio();
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ret = init_superio_ite();
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if (!ret) {
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buses_supported = CHIP_BUSTYPE_SPI;
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} else {
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buses_supported = CHIP_BUSTYPE_NONE;
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switch (superios[i].model) {
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case 0x8500:
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case 0x8502:
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case 0x8510:
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case 0x8511:
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case 0x8512:
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/* FIXME: This should be enabled, but we need a check
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* for laptop whitelisting due to the amount of things
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* which can go wrong if the EC firmware does not
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* implement the interface we want.
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*/
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//it85xx_spi_init(superios[i]);
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break;
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case 0x8705:
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ret |= it8705f_write_enable(superios[i].port);
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break;
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case 0x8716:
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case 0x8718:
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case 0x8720:
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ret |= it87spi_probe(superios[i].port);
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break;
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default:
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msg_pdbg("Super I/O ID 0x%04hx is not on the list of "
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"flash capable controllers.\n",
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superios[i].model);
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}
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}
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return ret;
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}
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@ -323,10 +329,13 @@ static int it8716f_spi_page_program(struct flashchip *flash, uint8_t *buf, int s
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*/
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int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len)
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{
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int total_size = 1024 * flash->total_size;
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fast_spi = 0;
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if ((programmer == PROGRAMMER_IT87SPI) || (total_size > 512 * 1024)) {
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/* FIXME: Check if someone explicitly requested to use IT87 SPI although
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* the mainboard does not use IT87 SPI translation. This should be done
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* via a programmer parameter for the internal programmer.
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*/
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if ((flash->total_size * 1024 > 512 * 1024)) {
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spi_read_chunked(flash, buf, start, len, 3);
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} else {
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read_memmapped(flash, buf, start, len);
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@ -343,9 +352,11 @@ int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start,
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* so page_size > 256 bytes needs a fallback.
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* FIXME: Split too big page writes into chunks IT87* can handle instead
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* of degrading to single-byte program.
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* FIXME: Check if someone explicitly requested to use IT87 SPI although
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* the mainboard does not use IT87 SPI translation. This should be done
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* via a programmer parameter for the internal programmer.
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*/
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if ((programmer == PROGRAMMER_IT87SPI) ||
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(flash->total_size * 1024 > 512 * 1024) ||
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if ((flash->total_size * 1024 > 512 * 1024) ||
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(flash->page_size > 256)) {
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spi_chip_write_1(flash, buf, start, len);
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} else {
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16
programmer.h
16
programmer.h
@ -52,11 +52,6 @@ enum programmer {
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#if CONFIG_ATAHPT == 1
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PROGRAMMER_ATAHPT,
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#endif
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#if CONFIG_INTERNAL == 1
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#if defined(__i386__) || defined(__x86_64__)
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PROGRAMMER_IT87SPI,
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#endif
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#endif
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#if CONFIG_FT2232_SPI == 1
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PROGRAMMER_FT2232_SPI,
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#endif
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@ -273,7 +268,8 @@ struct superio {
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uint16_t port;
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uint16_t model;
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};
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extern struct superio superio;
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extern struct superio superios[];
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extern int superio_count;
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#define SUPERIO_VENDOR_NONE 0x0
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#define SUPERIO_VENDOR_ITE 0x1
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struct pci_dev *pci_dev_find_filter(struct pci_filter filter);
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@ -289,6 +285,7 @@ extern int is_laptop;
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extern int force_boardenable;
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extern int force_boardmismatch;
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void probe_superio(void);
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int register_superio(struct superio s);
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int internal_init(void);
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int internal_shutdown(void);
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void internal_chip_writeb(uint8_t val, chipaddr addr);
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@ -582,10 +579,8 @@ int ich_spi_send_multicommand(struct spi_command *cmds);
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#endif
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/* it85spi.c */
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struct superio probe_superio_ite85xx(void);
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int it85xx_spi_init(void);
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int it85xx_spi_init(struct superio s);
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int it85xx_shutdown(void);
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int it85xx_probe_spi_flash(void);
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int it85xx_spi_send_command(unsigned int writecnt, unsigned int readcnt,
|
||||
const unsigned char *writearr, unsigned char *readarr);
|
||||
int it85_spi_read(struct flashchip *flash, uint8_t * buf, int start, int len);
|
||||
@ -594,9 +589,8 @@ int it85_spi_write_256(struct flashchip *flash, uint8_t * buf, int start, int le
|
||||
/* it87spi.c */
|
||||
void enter_conf_mode_ite(uint16_t port);
|
||||
void exit_conf_mode_ite(uint16_t port);
|
||||
struct superio probe_superio_ite(void);
|
||||
void probe_superio_ite(void);
|
||||
int init_superio_ite(void);
|
||||
int it87spi_init(void);
|
||||
int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt,
|
||||
const unsigned char *writearr, unsigned char *readarr);
|
||||
int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len);
|
||||
|
||||
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Reference in New Issue
Block a user