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Remove hardcoded wait from SPI write/erase routines and check the chip status register instead

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This has been tested by Harald Gutmann <harald.gutmann@gmx.net> with a
MX25L4005 chip.

Corresponding to flashrom svn r154 and coreboot v2 svn r2876.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
This commit is contained in:
Carl-Daniel Hailfinger 2007-10-18 17:56:42 +00:00
parent 67808fe9ca
commit 145acec2a3
1 changed files with 2 additions and 18 deletions
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20
spi.c
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@ -270,17 +270,9 @@ int generic_spi_chip_erase(struct flashchip *flash)
generic_spi_write_enable();
/* Send CE (Chip Erase) */
generic_spi_command(1, 0, cmd, NULL);
/* The chip needs some time for erasing, the MX25L4005A has a maximum
* time of 7.5 seconds.
* FIXME: Check the status register instead
* Do we have to check the status register before calling
* write_disable()? The data sheet suggests we don't have to call
* write_disable() at all because WEL is reset automatically.
/* Wait until the Write-In-Progress bit is cleared */
while (generic_spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
sleep(1);
*/
generic_spi_write_disable();
sleep(8);
return 0;
}
@ -294,17 +286,9 @@ void it8716f_spi_page_program(int block, uint8_t *buf, uint8_t *bios) {
bios[256 * block + i] = buf[256 * block + i];
}
outb(0, it8716f_flashport);
/* The chip needs some time for page program, the MX25L4005A has a
* maximum time of 5 ms.
* FIXME: Check the status register instead.
* Do we have to check the status register before calling
* write_disable()? The data sheet suggests we don't have to call
* write_disable() at all because WEL is reset automatically.
/* Wait until the Write-In-Progress bit is cleared */
while (generic_spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
usleep(1000);
*/
generic_spi_write_disable();
usleep(5000);
}
void generic_spi_page_program(int block, uint8_t *buf, uint8_t *bios)