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mirror of https://review.coreboot.org/flashrom.git synced 2025-04-29 16:03:47 +02:00

Rebased Board Enable Patch: Abit VT6X4

This board has *no* usable IDs at all, neither DMI nor PCI
subsystem IDs. You have to force it using "-m abit:vt6x4"

Try 3: really correct polarity of the GPIO

Corresponding to flashrom svn r950.

Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
Acked-by: Sean Nelson <audiohacked@gmail.com>
This commit is contained in:
Michael Karcher 2010-03-19 22:30:49 +00:00 committed by Sean Nelson
parent 49146c15a9
commit 187a46acd1

View File

@ -1018,6 +1018,14 @@ static int board_soyo_sy_7vca(const char *name)
return 0;
}
/**
* Suited for Abit VT6X5: Pro133x + VT82C686A
*/
static int via_apollo_gpo4_lower(const char *name)
{
return via_apollo_gpo_set(4, 0);
}
/**
* Enable some GPIO pin on SiS southbridge.
* Suited for MSI 651M-L: SiS651 / SiS962
@ -1263,6 +1271,7 @@ struct board_pciid_enable board_pciid_enables[] = {
/* first pci-id set [4], second pci-id set [4], dmi identifier coreboot id [2], vendor name board name max_rom_... OK? flash enable */
{0x8086, 0x2926, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, NULL, "Abit", "IP35", 0, OK, intel_ich_gpio16_raise},
{0x8086, 0x2930, 0x147b, 0x1083, 0x10ec, 0x8167, 0x147b, 0x1083, NULL, NULL, NULL, "Abit", "IP35 Pro", 0, OK, intel_ich_gpio16_raise},
{0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, NULL, "abit", "vt6x4", "Abit", "VT6X4", 0, NT, via_apollo_gpo4_lower},
{0x105a, 0x0d30, 0x105a, 0x4d33, 0x8086, 0x1130, 0x8086, 0, NULL, NULL, NULL, "Acorp", "6A815EPD", 0, OK, board_acorp_6a815epd},
{0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, NULL, "ASRock", "P4i65GV", 0, OK, intel_ich_gpio23_raise},
{0x1022, 0x746B, 0, 0, 0, 0, 0, 0, NULL, "AGAMI", "ARUMA", "agami", "Aruma", 0, OK, w83627hf_gpio24_raise_2e},