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flashchips/winbond.c: Add reg_bits for W25Q256JW

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Add reg_bits for W25Q256JW as per the datasheet. The register
definitions are same as W25Q256JW_DTR.

Datasheet: https://www.winbond.com/hq/support/documentation/levelOne.jsp?__locale=en&DocNo=DA00-W25Q256JW

BUG=b:376929528
TEST=Program and verify WP ranges

```
flashrom -p internal --wp-status
flashrom -p internal --wp-range 0x0,0x2000000
flashrom -p internal --wp-enable
flashrom -p internal --wp-status
```

Change-Id: I050754b28a90911a50f891869297524ce9a6720e
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/85323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Kapil Porwal 2025-01-30 11:41:14 +05:30 committed by Anastasia Klimchuk
parent 15e6b33743
commit 1b9bcdc99b
1 changed files with 13 additions and 2 deletions
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15
flashchips/winbond.c
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@ -655,8 +655,9 @@
.page_size = 256,
/* supports SFDP */
/* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44, read ID 0x4B */
.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA,
.tested = TEST_OK_PREW,
.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA | FEATURE_WRSR2
| FEATURE_WRSR3,
.tested = TEST_OK_PREWB,
.probe = PROBE_SPI_RDID,
.probe_timing = TIMING_ZERO,
.block_erasers =
@ -689,6 +690,16 @@
.write = SPI_CHIP_WRITE256,
.read = SPI_CHIP_READ,
.voltage = {1650, 1950},
.reg_bits =
{
.srp = {STATUS1, 7, RW},
.srl = {STATUS2, 0, RW},
.bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}},
.tb = {STATUS1, 6, RW},
.cmp = {STATUS2, 6, RW},
.wps = {STATUS3, 2, RW},
},
.decode_range = DECODE_RANGE_SPI25,
},
{