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mirror of https://review.coreboot.org/flashrom.git synced 2025-07-02 22:43:17 +02:00

tree/: Replace NULL-case of programmer_delay() with internal_delay

Replace `programmer_delay(NULL, [..])` calls with direct
`internal_delay([..])` dispatches explicitly. Custom driver
delays remain hooked as well as core flashrom logic. The
NULL base case of 'programmer_delay()' then becomes a condition
to validate for layering violations or invalid flash contexts.

Change-Id: I1da230804d5e8f47a6e281feb66f381514dc6861
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/68434
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Edward O'Callaghan
2022-10-17 12:31:59 +11:00
committed by Edward O'Callaghan
parent 78e421bdf7
commit 1e01eefcba
12 changed files with 44 additions and 32 deletions

View File

@ -213,7 +213,7 @@ static int nicintel_ee_write_word_i210(uint8_t *eebar, unsigned int addr, uint16
eewr |= BIT(EEWR_CMDV);
pci_mmio_writel(eewr, eebar + EEWR);
programmer_delay(NULL, 5);
internal_delay(5);
int i;
for (i = 0; i < MAX_ATTEMPTS; i++)
if (pci_mmio_readl(eebar + EEWR) & BIT(EEWR_DONE))
@ -338,7 +338,7 @@ static int nicintel_ee_ready(uint8_t *eebar)
nicintel_ee_bitbang(eebar, 0x00, &rdsr);
nicintel_ee_bitset(eebar, EEC, EE_CS, 1);
programmer_delay(NULL, 1);
internal_delay(1);
if (!(rdsr & SPI_SR_WIP)) {
return 0;
}
@ -379,7 +379,7 @@ static int nicintel_ee_write_82580(struct flashctx *flash, const uint8_t *buf, u
nicintel_ee_bitset(eebar, EEC, EE_CS, 0);
nicintel_ee_bitbang(eebar, JEDEC_WREN, NULL);
nicintel_ee_bitset(eebar, EEC, EE_CS, 1);
programmer_delay(NULL, 1);
internal_delay(1);
/* data */
nicintel_ee_bitset(eebar, EEC, EE_CS, 0);
@ -394,7 +394,7 @@ static int nicintel_ee_write_82580(struct flashctx *flash, const uint8_t *buf, u
break;
}
nicintel_ee_bitset(eebar, EEC, EE_CS, 1);
programmer_delay(NULL, 1);
internal_delay(1);
if (nicintel_ee_ready(eebar))
goto out;
}