mirror of
https://review.coreboot.org/flashrom.git
synced 2025-04-27 07:02:34 +02:00
Refactor SuperIO accesses
We had duplicated code under different names and even open-coded some functions in some places. wbsio_read/regval -> sio_read wbsio_write/regwrite -> sio_write wbsio_mask -> sio_mask board_biostar_p4m80_m4 now uses existing IT87 functions. Corresponding to flashrom svn r547. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Luc Verhaegen <libv@skynet.be>
This commit is contained in:
Carl-Daniel Hailfinger
parent
1fa386262c
commit
24c1a16030
@ -44,26 +44,26 @@ void w836xx_ext_leave(uint16_t port)
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OUTB(0xAA, port);
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}
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/* General functions for reading/writing Winbond Super I/Os. */
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unsigned char wbsio_read(uint16_t index, uint8_t reg)
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/* Generic Super I/O helper functions */
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uint8_t sio_read(uint16_t port, uint8_t reg)
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{
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OUTB(reg, index);
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return INB(index + 1);
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OUTB(reg, port);
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return INB(port + 1);
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}
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void wbsio_write(uint16_t index, uint8_t reg, uint8_t data)
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void sio_write(uint16_t port, uint8_t reg, uint8_t data)
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{
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OUTB(reg, index);
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OUTB(data, index + 1);
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OUTB(reg, port);
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OUTB(data, port + 1);
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}
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void wbsio_mask(uint16_t index, uint8_t reg, uint8_t data, uint8_t mask)
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void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask)
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{
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uint8_t tmp;
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OUTB(reg, index);
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tmp = INB(index + 1) & ~mask;
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OUTB(tmp | (data & mask), index + 1);
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OUTB(reg, port);
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tmp = INB(port + 1) & ~mask;
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OUTB(tmp | (data & mask), port + 1);
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}
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/**
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@ -73,30 +73,30 @@ void wbsio_mask(uint16_t index, uint8_t reg, uint8_t data, uint8_t mask)
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* - Agami Aruma
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* - IWILL DK8-HTX
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*/
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static int w83627hf_gpio24_raise(uint16_t index, const char *name)
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static int w83627hf_gpio24_raise(uint16_t port, const char *name)
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{
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w836xx_ext_enter(index);
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w836xx_ext_enter(port);
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/* Is this the W83627HF? */
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if (wbsio_read(index, 0x20) != 0x52) { /* Super I/O device ID reg. */
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if (sio_read(port, 0x20) != 0x52) { /* Super I/O device ID reg. */
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fprintf(stderr, "\nERROR: %s: W83627HF: Wrong ID: 0x%02X.\n",
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name, wbsio_read(index, 0x20));
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w836xx_ext_leave(index);
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name, sio_read(port, 0x20));
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w836xx_ext_leave(port);
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return -1;
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}
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/* PIN89S: WDTO/GP24 multiplex -> GPIO24 */
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wbsio_mask(index, 0x2B, 0x10, 0x10);
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sio_mask(port, 0x2B, 0x10, 0x10);
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/* Select logical device 8: GPIO port 2 */
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wbsio_write(index, 0x07, 0x08);
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sio_write(port, 0x07, 0x08);
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wbsio_mask(index, 0x30, 0x01, 0x01); /* Activate logical device. */
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wbsio_mask(index, 0xF0, 0x00, 0x10); /* GPIO24 -> output */
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wbsio_mask(index, 0xF2, 0x00, 0x10); /* Clear GPIO24 inversion */
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wbsio_mask(index, 0xF1, 0x10, 0x10); /* Raise GPIO24 */
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sio_mask(port, 0x30, 0x01, 0x01); /* Activate logical device. */
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sio_mask(port, 0xF0, 0x00, 0x10); /* GPIO24 -> output */
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sio_mask(port, 0xF2, 0x00, 0x10); /* Clear GPIO24 inversion */
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sio_mask(port, 0xF1, 0x10, 0x10); /* Raise GPIO24 */
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w836xx_ext_leave(index);
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w836xx_ext_leave(port);
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return 0;
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}
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@ -113,27 +113,27 @@ static int w83627hf_gpio24_raise_2e(const char *name)
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* - MSI K8T Neo2-F
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* - MSI K8N-NEO3
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*/
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static int w83627thf_gpio4_4_raise(uint16_t index, const char *name)
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static int w83627thf_gpio4_4_raise(uint16_t port, const char *name)
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{
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w836xx_ext_enter(index);
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w836xx_ext_enter(port);
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/* Is this the W83627THF? */
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if (wbsio_read(index, 0x20) != 0x82) { /* Super I/O device ID reg. */
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if (sio_read(port, 0x20) != 0x82) { /* Super I/O device ID reg. */
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fprintf(stderr, "\nERROR: %s: W83627THF: Wrong ID: 0x%02X.\n",
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name, wbsio_read(index, 0x20));
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w836xx_ext_leave(index);
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name, sio_read(port, 0x20));
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w836xx_ext_leave(port);
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return -1;
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}
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/* PINxxxxS: GPIO4/bit 4 multiplex -> GPIOXXX */
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wbsio_write(index, 0x07, 0x09); /* Select LDN 9: GPIO port 4 */
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wbsio_mask(index, 0x30, 0x02, 0x02); /* Activate logical device. */
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wbsio_mask(index, 0xF4, 0x00, 0x10); /* GPIO4 bit 4 -> output */
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wbsio_mask(index, 0xF6, 0x00, 0x10); /* Clear GPIO4 bit 4 inversion */
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wbsio_mask(index, 0xF5, 0x10, 0x10); /* Raise GPIO4 bit 4 */
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sio_write(port, 0x07, 0x09); /* Select LDN 9: GPIO port 4 */
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sio_mask(port, 0x30, 0x02, 0x02); /* Activate logical device. */
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sio_mask(port, 0xF4, 0x00, 0x10); /* GPIO4 bit 4 -> output */
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sio_mask(port, 0xF6, 0x00, 0x10); /* Clear GPIO4 bit 4 inversion */
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sio_mask(port, 0xF5, 0x10, 0x10); /* Raise GPIO4 bit 4 */
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w836xx_ext_leave(index);
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w836xx_ext_leave(port);
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return 0;
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}
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@ -151,14 +151,14 @@ static int w83627thf_gpio4_4_raise_4e(const char *name)
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/**
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* w83627: Enable MEMW# and set ROM size to max.
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*/
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static void w836xx_memw_enable(uint16_t index)
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static void w836xx_memw_enable(uint16_t port)
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{
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w836xx_ext_enter(index);
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if (!(wbsio_read(index, 0x24) & 0x02)) { /* Flash ROM enabled? */
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w836xx_ext_enter(port);
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if (!(sio_read(port, 0x24) & 0x02)) { /* Flash ROM enabled? */
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/* Enable MEMW# and set ROM size select to max. (4M). */
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wbsio_mask(index, 0x24, 0x28, 0x28);
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sio_mask(port, 0x24, 0x28, 0x28);
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}
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w836xx_ext_leave(index);
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w836xx_ext_leave(port);
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}
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/**
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@ -595,21 +595,18 @@ static int board_kontron_986lcd_m(const char *name)
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static int board_biostar_p4m80_m4(const char *name)
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{
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/* enter IT87xx conf mode */
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OUTB(0x87, 0x2e);
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OUTB(0x01, 0x2e);
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OUTB(0x55, 0x2e);
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OUTB(0x55, 0x2e);
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enter_conf_mode_ite(0x2e);
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/* select right flash chip */
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wbsio_mask(0x2e, 0x22, 0x80, 0x80);
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sio_mask(0x2e, 0x22, 0x80, 0x80);
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/* bit 3: flash chip write enable
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* bit 7: map flash chip at 1MB-128K (why though? ignoring this.)
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*/
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wbsio_mask(0x2e, 0x24, 0x04, 0x04);
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sio_mask(0x2e, 0x24, 0x04, 0x04);
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/* exit IT87xx conf mode */
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wbsio_write(0x2e, 0x02, 0x02);
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exit_conf_mode_ite(0x2e);
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return 0;
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}
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8
flash.h
8
flash.h
@ -579,9 +579,9 @@ void print_supported_pcidevs(struct pcidev_status *devs);
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/* board_enable.c */
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void w836xx_ext_enter(uint16_t port);
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void w836xx_ext_leave(uint16_t port);
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unsigned char wbsio_read(uint16_t index, uint8_t reg);
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void wbsio_write(uint16_t index, uint8_t reg, uint8_t data);
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void wbsio_mask(uint16_t index, uint8_t reg, uint8_t data, uint8_t mask);
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uint8_t sio_read(uint16_t port, uint8_t reg);
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void sio_write(uint16_t port, uint8_t reg, uint8_t data);
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void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask);
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int board_flash_enable(const char *vendor, const char *part);
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void print_supported_boards(void);
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@ -737,6 +737,8 @@ int ich_spi_write_256(struct flashchip *flash, uint8_t * buf);
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/* it87spi.c */
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extern uint16_t it8716f_flashport;
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void enter_conf_mode_ite(uint16_t port);
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void exit_conf_mode_ite(uint16_t port);
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int it87xx_probe_spi_flash(const char *name);
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int it8716f_spi_command(unsigned int writecnt, unsigned int readcnt,
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const unsigned char *writearr, unsigned char *readarr);
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33
it87spi.c
33
it87spi.c
@ -34,23 +34,10 @@ uint16_t it8716f_flashport = 0;
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/* use fast 33MHz SPI (<>0) or slow 16MHz (0) */
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int fast_spi = 1;
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/* Generic Super I/O helper functions */
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uint8_t regval(uint16_t port, uint8_t reg)
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{
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OUTB(reg, port);
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return INB(port + 1);
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}
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void regwrite(uint16_t port, uint8_t reg, uint8_t val)
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{
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OUTB(reg, port);
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OUTB(val, port + 1);
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}
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/* Helper functions for most recent ITE IT87xx Super I/O chips */
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#define CHIP_ID_BYTE1_REG 0x20
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#define CHIP_ID_BYTE2_REG 0x21
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static void enter_conf_mode_ite(uint16_t port)
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void enter_conf_mode_ite(uint16_t port)
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{
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OUTB(0x87, port);
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OUTB(0x01, port);
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@ -61,9 +48,9 @@ static void enter_conf_mode_ite(uint16_t port)
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OUTB(0xaa, port);
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}
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static void exit_conf_mode_ite(uint16_t port)
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void exit_conf_mode_ite(uint16_t port)
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{
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regwrite(port, 0x02, 0x02);
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sio_write(port, 0x02, 0x02);
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}
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static uint16_t find_ite_spi_flash_port(uint16_t port)
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@ -73,13 +60,13 @@ static uint16_t find_ite_spi_flash_port(uint16_t port)
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enter_conf_mode_ite(port);
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id = regval(port, CHIP_ID_BYTE1_REG) << 8;
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id |= regval(port, CHIP_ID_BYTE2_REG);
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id = sio_read(port, CHIP_ID_BYTE1_REG) << 8;
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id |= sio_read(port, CHIP_ID_BYTE2_REG);
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/* TODO: Handle more IT87xx if they support flash translation */
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if (0x8716 == id || 0x8718 == id) {
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/* NOLDN, reg 0x24, mask out lowest bit (suspend) */
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tmp = regval(port, 0x24) & 0xFE;
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tmp = sio_read(port, 0x24) & 0xFE;
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printf("Serial flash segment 0x%08x-0x%08x %sabled\n",
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0xFFFE0000, 0xFFFFFFFF, (tmp & 1 << 1) ? "en" : "dis");
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printf("Serial flash segment 0x%08x-0x%08x %sabled\n",
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@ -94,13 +81,13 @@ static uint16_t find_ite_spi_flash_port(uint16_t port)
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if ((tmp & 0xe) && (!(tmp & 1 << 4))) {
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printf("Enabling LPC write to serial flash\n");
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tmp |= 1 << 4;
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regwrite(port, 0x24, tmp);
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sio_write(port, 0x24, tmp);
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}
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printf("serial flash pin %i\n", (tmp & 1 << 5) ? 87 : 29);
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/* LDN 0x7, reg 0x64/0x65 */
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regwrite(port, 0x07, 0x7);
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flashport = regval(port, 0x64) << 8;
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flashport |= regval(port, 0x65);
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sio_write(port, 0x07, 0x7);
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flashport = sio_read(port, 0x64) << 8;
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flashport |= sio_read(port, 0x65);
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}
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exit_conf_mode_ite(port);
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return flashport;
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10
wbsio_spi.c
10
wbsio_spi.c
@ -32,24 +32,24 @@ static uint16_t wbsio_get_spibase(uint16_t port)
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uint16_t flashport = 0;
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w836xx_ext_enter(port);
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id = wbsio_read(port, 0x20);
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id = sio_read(port, 0x20);
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if (id != 0xa0) {
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fprintf(stderr, "\nW83627 not found at 0x%x, id=0x%02x want=0xa0.\n", port, id);
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goto done;
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}
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if (0 == (wbsio_read(port, 0x24) & 2)) {
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if (0 == (sio_read(port, 0x24) & 2)) {
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fprintf(stderr, "\nW83627 found at 0x%x, but SPI pins are not enabled. (CR[0x24] bit 1=0)\n", port);
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goto done;
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}
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wbsio_write(port, 0x07, 0x06);
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if (0 == (wbsio_read(port, 0x30) & 1)) {
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sio_write(port, 0x07, 0x06);
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if (0 == (sio_read(port, 0x30) & 1)) {
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fprintf(stderr, "\nW83627 found at 0x%x, but SPI is not enabled. (LDN6[0x30] bit 0=0)\n", port);
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goto done;
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}
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flashport = (wbsio_read(port, 0x62) << 8) | wbsio_read(port, 0x63);
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flashport = (sio_read(port, 0x62) << 8) | sio_read(port, 0x63);
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done:
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w836xx_ext_leave(port);
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